UVM: Now or Never?

Date: Wednesday June 6
Time: 12.00pm - 1.30pm
Venue: Moscone Center, San Francisco
Room: East Mezzanine Level, Room 220

You are invited to a free Easier UVM solutions workshop.

Doulos CTO John Aynsley will highlight the reasons why you should (or in a few cases should not) be adopting UVM right now, and explain how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL. He will explore some of the practicalities of migrating to UVM from other methodologies, discuss using UVM alongside C/SystemC reference models, and introduce register modeling using the UVM register layer.

Register by June 5th, and qualify to receive a FREE* copy of the UVM Golden Reference Guide - the essential project reference .

Find out more about Easier UVM

ON-LINE REGISTRATION IS NOW CLOSED - PLEASE VISIT THE DOULOS BOOTH #1501 FOR ANY LAST MINUTE BOOKINGS FOR THIS WORKSHOP - THANK YOU


(*first 50 registrations only)