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In recent years the use of functional coverage has become the dominant method for managing the verification process for large SoC developments. However this has been mainly in the ASIC arena, using SystemVerilog-based methodologies such as OVM and VMM. Of course there are also large SoCs being designed using Field Programmable Gate Arrays (FPGAs) - in fact there is a concentration of advanced FPGA users on the US East Coast, in the military/aerospace sector: and many of them are using VHDL. This then raises the question of how to use functional coverage in the older yet still popular HDLs; is it possible to implement functional coverage in a usable and efficient way without using SystemVerilog?
We will start with a short overview of functional coverage and its application.
The main body of the paper uses VHDL as an example, and shows how functional coverage may be collected. Firstly we look at an example of how either PSL or SVA coverpoints may be bound to VHDL code, and coverage data stored in proprietary format (a technique which is also applicable to both Verilog and SystemC).
Then we investigate how to write functional coverage information using concurrent procedure calls together with VHDL attributes. We will show the VHDL language features for data assignment monitoring and introspection which allow a file of coverage information to be stored. We will show how to post-process data in the text file for injection into a proprietary database format; and also how to make sure that the cover points do not affect synthesis when embedded in RTL code.
We will see if we can reduce the overhead of coverage collection by keeping VHDL coverage information in memory. We will investigate how the XML UCDB interchange format specified at the Verification Academy can be written out directly from VHDL for injection into a coverage database at the end of simulation.
We conclude with a brief discussion of how similar techniques could be implemented in Verilog and SystemC.
This paper will be of interest to designers of large SoCs who believe in functional coverage, but who do not currently have access to SystemVerilog.
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