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ARM Cortex-M0+ System Design

Standard Level - 3 days

ARM® Cortex®-M0+ System Design is a 3-day class for software/hardware and verification engineers developing or supporting Cortex-M0+ based Systems on Chips. The course covers the ARM Cortex-M0+ programmer's model, instruction set architecture as well as hardware intergration, system interfaces, power management and debug infrastructure.

Who should attend?

Design teams working on the integration and verification of an ARM Cortex-M0+ based core.

Pre-requisites
  • Some knowledge of embedded systems.
  • A basic awareness of ARM is useful but not essential.
  • Knowledge of programming in C.
  • Experience of assembler programming is not required but would be beneficial.
Training materials

This class uses training materials developed by ARM®

Content

Day 1

Introduction to ARM

Cortex-M0+ Overview

Tools Overview for ARM Microcontrollers

Toolchain • Models • Debug & Trace • Development Boards 


v6-M Programmer’s Model

Data types • Core registers • Modes • Exceptions • Instruction • Set Overview 

v6-M Memory Model

System Caches • Write Buffers • TCMs • Memory Types • Endianness • Address Map 

Day 2

v6-M Exception Handling

Exception Model • Interrupts • Interrupt Handling • Prioritization and Control • Writing the Vector Table and Interrupt Handlers • Internal Interrupts and RTOS Support • Fault Exceptions 

v6-M Compiler Hints and Tips

Basic Compilation • Compiler Optimizations • Coding Considerations • Mixing C/C++ and Assembler • Local and Global Data issues 

CMSIS Overview

CMSIS-CORE • CMSIS-DSP • CMSIS-RTOS • CMSIS-SVD • CMSIS-DAP 

SysTick Timer

Built-in Functions • Calibration Examples 

Day 3

AMBA AHB-Lite

AHB Evolution • AHB-Lite Bus Protocol • AHB Signals 

Processor Core

Processor Pipeline • Instruction Execution 

System Interfaces

Memory System Bus Interfaces Details • Processor and Integration Levels 

Integration Example

Wake-up Interrupt Controller • Debug Access Port • Micro Trace Buffer • Clock Gating 

Power Management

Architectural Clock Gates • Sleep Modes • Power Domains • System Control 

Cortex-M0+ Debug

Introduction to Debug • Debug Access Port (DAP) • Breakpoints/Watchpoints & Vector Catch • Cortex-M0+ Debug • System Control 

Memory Protection

Memory Types • Memory attributes • Memory Protection Regions Configurations 

Trace

MTB Operations • Register Description • Signal Description • Implementation Issues 

Implementation and Integration

RTL Configuration • Design Flow Step • Reference Methodologies ARM and Cortex-M0+ are registered trade marks of ARM Holdings Plc.

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