Foundation level - 4 sessions
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content as a scheduled in-person class and delivers comparable learning outcomes. Daily sessions comprise 4-6 hours of class contact time.
Essential Digital Design Techniques is a fast-track, application orientated course designed to bridge the gap between text book theory and real world digital design practice.
It significantly accelerates the on-the-job learning curve for engineers new to digital design, or those needing to refine their design skills before project involvement. With a strong emphasis on practical design and hands-on workshops, this course has been specifically developed to capture design techniques usually learned over months, in an intensive 2-day format.
Essential Digital Design Techniques provides the ideal first stage in full scale project training for graduate design engineers, or engineers moving into digital design from other disciplines (including software or analog design). As such, it is the natural precursor to the Doulos Comprehensive VHDL and Comprehensive Verilog courses, which prepare engineers for HDL application within FPGA or ASIC design projects.
- New graduate engineers embarking on a first project, or engineers with limited practical experience of digital design.
- Engineers from other disciplines (e.g. software design or analog design) re-training for digital design involvement, or requiring familiarisation with modern digital design techniques.
Delegates require no prior involvement in digital design projects or HDL knowledge, but should be familiar with the basic principles of digital electronics. Some background refresher reading can be suggested prior to the course if required (contact Doulos for details, or to discuss course suitability).
- Combinational and Sequential Logic Design for PLDs and ASICs, with an emphasis on synchronous design techniques
- How to design and implement fundamental structures e.g. decoders, multiplexers, shift registers, counters
- How to design and implement synchronous Finite State Machines
- An overview of ASIC and field programmable logic design including a survey of state of the art devices
- Designing with programmable devices
- Effective Design methodologies and flows
PLEASE NOTE: this course does not teach, or require knowledge in a specific Hardware Description Language.
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Course Fees include:
- Fully indexed course notes creating a complete reference manual
- Workbook full of practical examples and solutions to help you apply your knowledge
- Representing data using electronics
- Advantages of digital design over software and analog hardware
- Basic design flow and software tools
- Introducing Hardware Description Languages (HDLs)
Digital Design Basics
- Boolean algebra
- Combinational logic
- Implementing logic gates in hardware
- Asynchronous sequential logic
- Sequential logic, clocks and flip-flops
- Implementing sequential logic in hardware
- Timing violations
- Safe design rules
- Static timing analysis
- Types of flip-fop
Digital Design Technologies
- Application Specific Integrated Circuits (ASICs)
- Evolution of Programmable Logic Devices
- Volatile and non-volatile technologies
- Economic considerations
- Choosing between different technologies and devices
- Representing combinational logic in HDLs
- Representing sequential logic in HDLs
- Resource sharing
- Scalable design
- Design trade-offs
- Introducing verification
- Encoders and decoders
- Priority encoders
- Parity generator
- Shift Registers
- Johnson (ring) "counters"
- Linear Feedback Shift Registers
- Unsigned and two's complement arithmetic
- Half and full adders
- Large adders
- Carry lookahead adder
- Synthesis of adders
- Wide counters
- Binary to BCD conversion
- Serial arithmetic
Outside the Synchronous World
- Representing digital logic using analog components
- Inputs hazards and metastability
- Three-state buses
- Pin locking
- Working safely with clocks and resets
- I/O buffers and I/O standards
- Ground bounce, termination and other analog issues
Finite State Machines and IP Blocks
- Graphical entry and symbolism
- Moore and Mealy structures
- State encoding and optimisation
- Using HDLs to design FSMs
- Using memories
- Memory types
- Using other complex functions