Die Kursteilnehmer benötigen keine Vorkenntnisse in Verifikation, ihnen sollte allerdings der digitale Designprozess geläufig sein. Kenntnisse in Hardwarebeschreibungssprachen (HDL) order anderen Sprachen in Verbindung mit Verifikation, wie z.B. e oder PSL, sind hilfreich aber nicht unerlässlich.
Die Doulos Kursunterlagen sind für ihren umfassenden Informationsgehalt und die äußerst benutzerfreundliche Präsentation allgemein bekannt. In den Kursgebühren ist enthalten:
Definitions, terminology • Functional verification flow and methods • Linting • Simulation • Debugging • Modelling • Coverage • Assertion-based verification • Formal methods
Verification Plan: Creation and maintenance • Verification strategy • Test definition, generation and execution • Re-usable verification IP • Milestones and code reviews • Regression and stress testing • Verification metrics and bug-tracking
HDL testbenches • Testbench architecture • Bus Functional Models and data modelling • Testbench automation • Hardware Verification Languages (HVLs) • Object-oriented and aspect-oriented programming • Stimulus generation, directed, random and constrained-random • Response checking and self-checking testbenches • Variable latency, FIFOs and scoreboarding • Coverage-driven methodology and types of coverage
Properties, their definition and use • Temporal properties • Assertions • Authoring of properties and assertions • Observability and functional coverage • Re-using properties
Definitions, motivation and terminology • Equivalence checking • Property checking • Coverage • Safety, liveness, invariant • Assumptions • Dynamic formal verification
Hardware acceleration • Emulation and In-Circuit-Emulation (ICE) • FPGA Prototyping • Observability of internal design nodes • Synthesizable assertions
Boolean algebra • Temporal logic: CTL and LTL • Fairness
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