Kursteilnehmer müssen an Essential Digital Design Techniques (oder gleichwertigem Training) teilgenommen haben oder gutes praktisches Grundwissen in digitalem Design mitbringen. Vorkenntnisse in VHDL oder Erfahrungen mit einer Softwaresprache sind nicht erforderlich.
Teilnehmer des Moduls Advanced VHDL müssen über grundlegende Erfahrung im Hardwaredesign verfügen und das Modul VHDL for Designers oder ein gleichwertiges Training absolviert haben. Wir haben die Erfahrung gemacht, dass Kursteilnehmer ihre Vorkenntnisse oft überschätzt haben. Wenn Sie sich nicht sicher sind, ist es wahrscheinlich am besten, am kompletten Comprehensive VHDL Training teilzunehmen.
The scope and application of VHDL • Design and tool flow • FPGAs • The VHDL world
The basic VHDL language constructs • VHDL source files and libraries • The compilation procedure • Synchronous design and timing constraints
Simulation • Synthesis • Place-and-Route • Device programming
Entities and Architectures • Std_logic • Signals and Ports • Concurrent assignments • Instantiation and Port Maps • The Context Clause
The Process statement • Sensitivity list versus Wait • Signal assignments and delta delays • Register transfers • Default assignment • Simple Testbenches
If statements • Conditional signal assignments and Equivalent process • Transparent latches • Case statements • Synthesis of combinational logic
VHDL types • Standard packages • Integer subtypes • Std_logic and std_logic_vector • Slices and concatenation • Integer and vector values
Arithmetic operator overloading • Arithmetic packages • Mixing integers and vectors • Resizing vectors • Resource sharing
RISING_EDGE • Asynchronous set or reset • Synchronous inputs and clock enables • Synthesisable process templates • Implying registers
Enumeration types • VHDL coding styles for FSMs • State encoding • Unreachable states and input hazards
Array types • Modelling memories • IP Generators • Instantiating generated components • Implementing ROMs
TEXTIO • READ and WRITE • Using TEXTIO for testbench stimulus and outputs • STD_LOGIC_TEXTIO
Variables • Loops • Std_logic and resolution • Array and integer subtypes • Aggregates
Hierarchical design flow • Library name mapping • Component declaration • Configuration • Hierarchical configurations • Compilation order
Array and type attributes • Port Maps • Generics and Generic Maps • Generate statement • Generics and generate
Subprograms • Procedures • Functions • Parameters and Parameter Association • Package declarations • Package bodies • Subprograms in packages • Subprogram overloading • Operator overloading • Qualified expressions • RTL Procedures
Assertions • Opening and closing files • Catching TEXTIO errors • Converting between VHDL types and strings • Checking simulation results • Initialising memories • Foreign bodies
Rationale for gate level simulation • VITAL tool flow • Reuse of RTL testbench at gate level • Comparison of RTL and gate level results • Behavioural modelling
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