PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content as a scheduled in-person class and delivers comparable learning outcomes. Daily sessions comprise 4-6 hours of class contact time.
FPGA designers and logic designers
Sessions 1 + 2
Sessions 3 + 4
Lab 1: Transceiver Core Generation – Use the Transceivers Wizard to create instantiation templates.
Lab 2: Transceiver Simulation – Simulate the transceiver IP by using the IP example design.
Lab 3: 64B/66B Encoding – Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.
Lab 4: Transceiver Implementation – Implement the transceiver IP by using the IP example design.
Lab 5: IBERT Design – Verify transceiver links on real hardware.
Lab 6: Transceiver Debugging – Debug transceiver links.
Complete an enquiry form and a Doulos representative will get back to you.
Enquiry FormPrice on request