Standard Level - 3 days
Use the ISE® software tools to implement an FPGA design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.
This course covers ISE software features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents and global timing constraints.
This course incorporates material from "Designing for Performance" which will enable you to optimize your design for implementation in a smaller FPGA or a lower speed grade to reduce system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time and lower development costs.
Digital and ASIC designers who are interested in FPGA design training and have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
- Working HDL knowledge (VHDL or Verilog)
- Digital design experience
- Xilinx ISE Design Suite: Logic or System Edition: Version 14.1
- Architecture: 7 series FPGAs*
- Demo board: Kintex™-7 KC705 board*
*Please contact Doulos for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will know how to:
- Take advantage of the primary features of the FPGA under demo
- Use the Xilinx Project Navigator to implement and simulate an FPGA design
- Read reports and determine whether your design goals were met
- Use the Clocking Wizard to create DCM instantiations
- Use the I/O Planner to make good pin assignments
- Use the Xilinx Constraints Editor to enter global timing constraints
- Describe the architectural features of the FPGA under demo
- Create and integrate cores into your design flow by using the CORE Generator™ software system
- Identify the different members of the 7 series families
- Describe the clocking features of the FPGA under demo and how it can be used to improve performance
- Increase performance by duplicating registers and pipelining
- Increase system reliability by adding an appropriate synchronization circuit
- Describe different synthesis options and how they can improve performance
- Describe a flow for obtaining timing closure
- Pinpoint design bottlenecks by using Timing Analyzer reports
- Apply advanced timing constraints to meet your performance goals
- Use advanced implementation options to increase design performance
- Course Agenda
- Basic FPGA Architecture
- Xilinx Tool Flow
- Lab 1: Xilinx Tool Flow
- Reading Reports
- Lab 2: Clocking Wizard and Pin Assignment
- Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool
- Global Timing Constraints
- Lab 4: Global Timing Constraints
- Synchronous Design Techniques
- Course Summary
- Review of Essentials of FPGA Design
- Designing with FPGA Resources
- CORE Generator Software System
- Basic FPGA Clock Resources
- FPGA Clock Resources of the FPGA under demo
- Lab 5: Designing with FPGA Resources
- FPGA Design Techniques
- Synthesis Techniques
- Lab 6: Synthesis Techniques
- Achieving Timing Closure
- Lab 7: Review of Global Timing Constraints
- Path-Specific Timing Constraints, Part 1
- Path-Specific Timing Constraints, Part 2
- Lab 8: Achieving Timing Closure
- Advanced Implementation Options
- Lab 9: Designing for Performance
- Lab 10: FPGA Editor Demo (optional)
- ChipScope Pro Software (optional)
- Lab 11: ChipScope Pro Software (optional)
- Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to the demo board.
- Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.
- Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead tool. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules.
- Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.
- Lab 5: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.
- Lab 6: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results.
- Lab 7: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
- Lab 8: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.
- Lab 9: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.
- Lab 10: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.
- Lab 11: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.