PLEASE NOTE: This is a ONLINE SELF-PACED training.
Fast-track Verilog for VHDL Users is an intensive 16 hour conversion-training course teaching the application of the Verilog® Hardware Description Language for programmable logic and ASIC design. It is not suitable for engineers who haven’t already attended the Comprehensive VHDL course or are not well practised in VHDL based design.
By emphasising the similarities and highlighting the differences between the VHDL and Verilog languages and the associated design flows, this course fast-tracks delegates through the Verilog learning curve. It is designed to enable VHDL based engineers to be Verilog-ready for transition to SystemVerilog application.
The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools. A number of supplementary topics are also available, including a preparatory overview of SystemVerilog.
Workshops comprise approximately 50% of class time and are based around carefully designed exercises to reinforce and challenge the extent of learning. Because Doulos is an independent company, our clients can choose the design tools used during the workshops.
Delegates must have attended the Doulos Comprehensive VHDL course (or equivalent) and have a good working knowledge of VHDL and digital hardware design. No previous knowledge of Verilog is required.
Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include
What is Verilog? • Brief history and current status • The PLI • Scope of Verilog • Design flow • Verilog-2001 • SystemVerilog • Verilog books and Internet resources
“Philosophy” • Red Tape • Strong typing • Determinisim • Data abstraction • Structure vs behaviour – Nets vs registers • Language structure – architecture, packages, configurations, files • Identifiers • Output ports • Implicit wires • Arrays • Aggregates • Signedness • Operators • Signal vs variables/nets • Process vs initial/always • if, case, loop differences • File i/o • Hierarchical names
Modules & ports • Continuous assignments • Comments • Names • Nets and strengths • Design hierarchy • Module instances • Primitive instances • Text fixtures • $monitor • Initial blocks • Logic values • Vectors • Registers • Numbers • Output formatting • Timescales • Always blocks • $stop and $finish • Using nets and variables correctly
Event control • If statements • Begin-endw Incomplete assignment and latches • Unknown and don’t care • Conditional operator • Tristates • Case, casez and casex statements • full_case and parellel_case directives • For, repeat, while and forever loops • integers • Self-disabling blocks • Combinational logic synthesis
Synthesising flip-flops & latches • Avoiding simulation race hazards • Nonblocking assignments • Asynchronous & synchronous resets • Clock enables • Synthesizable always templates
Verilog operators • Part selects • Concatenation & replication • Shift registers • Conditional compilation • Parameterisation and generate • Hierarchical names • Arithmetic operators and their synthesis • Signed and unsigned values • Memory arrays • RAM modelling and synthesis • $readmemb and $readmemh
Understanding tasks • Task arguments • Task synchronization • Tasks and synthesis • Functions
File I/O – Writing to files; File access using MCDs; Reading from files • Automated design verification using Verilog • Force and release • Gate-level simulation • Back annotation using SDF • “Traditional” Verilog libraries • Configuration and libraries • Command-line options • Behavioural modelling
Algorithmic coding • Synchronization using waits & event control • Concurrent-disabling of always blocks • Named events • Fork & join • High-level modelling using tasks, Implicit FSMs and concurrent-disabling • Understanding intra-assignment controls • Overcoming clock skew • Blocking and nonblocking assignments • Continuous procedural assignment
Structural Verilog • Using built-in primitives • Net types & drive strengths • UDPs Gate, net & path delays • Specify blocks • Smart paths • Pulse rejection • Cell library modelling
Background • Who is SystemVerilog for? • Current status of SystemVerilog • RTL enhancements • Interfaces • Assertions • Testbenches • C interface
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