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Introduction to SystemVerilog SELF-PACED

Standard Level - 16 hours (estimated completion time)

PLEASE NOTE: This is a ONLINE SELF-PACED training.

Course Overview

SystemVerilog (IEEE 1800™), the successor to the Verilog® hardware description language, has become the dominant language standard for functional verification. SystemVerilog significantly enhances the capabilities of Verilog in a number of areas, offering productivity improvements for RTL designers, assertions, and constrained random stimulus generation for verification engineers. 

Introduction to SystemVerilog  teaches the basics of the SystemVerilog language that are useful for both design and directed test verification.

From an overview of the language and its evolution, the training provides a foundation for learning SystemVerilog from basic principles, to the synthesizable RTL language features.

This training is only available via the Doulos Thinkific Learning Portal. Please contact your local Doulos team to discuss your training needs and how to access the course. 

Select the drop-down blocks below to find out more.

  • Design engineers who wish to make full use of SystemVerilog's class-based verification capabilities for test bench development as well as learning SystemVerilog for RTL design.
  • Verification engineers aiming to deploy coverage driven verification approaches for the first time using SystemVerilog
  • Verification engineers wishing to migrate to SystemVerilog class-based verification from other established verification languages and test bench automation techniques
  • Engineers and managers who wish to evaluate the full range of SystemVerilog's capabilities for design and verification
  • EDA support engineers who wish to gain a comprehensive understanding of how their customers' engineering teams can most productively use SystemVerilog in both design and verification domains
  • The training lays the foundation for learning the SystemVerilog language for design and for verification.

  • The course teaches the synthesizable RTL language features of SystemVerilog. For hardware designers, this assumes an understanding of RTL synthesis with Verilog or VHDL. For verification engineers, this provides some familiarity with the RTL constructs as used by hardware designers.

A good working knowledge of Verilog is essential:

  • For engineers with no HDL knowledge or experience the Doulos Comprehensive Verilog course, or equivalent, is an essential precursor.
  • For engineers with no Verilog knowledge, but with working experience of VHDL, Doulos offer a Fast Track Verilog for VHDL Users class in a format tailored to equip delegates with the necessary foundation for SystemVerilog.
  • For onsite courses, precursor training in Verilog can be tailored to the specific team profile and combined with appropriate SystemVerilog modules to fully address team needs (see Modular SystemVerilog).

If you require any of these precursor training options please contact the Doulos team to discuss what will best suit your needs, or complete an online enquiry.

Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include

  • Fully indexed class notes creating a complete reference manual
  • Workbook full of practical examples and solutions to help you apply your knowledge
  • Access to course exercises and worked solutions on the free and open EDA Playground platform.  

Introduction

What is SystemVerilog? • Language evolution • Language features • Modules, ports, and parameters • Standard verification methodologies • References

Programming Language Features

Static and automatic variables • Increment and assignment operators • Labelling blocks • Time units • Do While and Assert • Task and function syntax • Strings and $sformat

Basic Data Types

4-state and 2-state types • Enumerations • Structs and unions • Packed and unpacked types • Multidimensional arrays • Packages and import

Interfaces

Interfaces • Ports and parameters on interfaces • Modports • Generic interface ports

RTL Processes

Register Transfer Level • always_comb, always_ff, always_latch • priority and unique • Wild equality

RTL Types

Synthesizable data types • Enums • Packed structs, unions, and arrays • Packages, ports and parameters • Synthesis of interfaces

Clocking Blocks

Clocking Blocks • Input and output skew • Clocking drives and synchronization • #1step sampling • Signal aliasing • Clocking blocks versus programs

Arrays and Queues

Dynamic Arrays • Queues • Associative Arrays

Bus-Functional Modeling

Bus-Functional Modeling • Separate Test from Test Harness • Tasks/functions in interfaces

Randomization

Testbench Automation • Random numbers in SystemVerilog • Randomize with inline constraints • Random stability

Coverage

Testbench Automation • Covergroups • Coverpoints • Cross coverage • Coverage bins

Other Language Features

$root and $unit • Enumeration methods • Multidimensional arrays • Assignment patterns • Array querying functions • Bit-stream casting

The Direct Programming Interface

DPI flow and simulator switches • Importing and exporting tasks and functions • Passing data between C and SystemVerilog • Open arrays • Pure and context tasks and functions

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