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Designing with the Versal Adaptive SoC: Hardware Debug ONLINE WORKSHOP

Standard Level - 2 sessions (4 hours per session including breaks)

With thanks to AMD for sponsoring this workshop:
It is available to attend FREE OF CHARGE (Usual price $990)

October 24 & 25 2024 - EurAsia - Register now »

October 24 & 25 2024 - Americas - Register now »

The Versal™ adaptive SoC from AMD is multi-featured, offering unprecedented system level performance and integration. 

Join us for a workshop which explores the tools and techniques available to debug AMD Versal™ devices. We'll investigate debugging the fabric and hard blocks as well as APIs which provide a Python interface for programming and debugging.

The workshop is designed to maximize individual engagement and learning.  Each attendee is encouraged to informally ask pertinent questions throughout, to actively participate in the learning process. 

Hardware developers, system architects
and anyone who wants to learn about the tools and techniques available to debug Versal adaptive SoC devices.

The workshop will provide you with an understanding of:

  • The different tool flows for AMD Versal devices
  • The debug interfaces in the Versal devices
  • The different debug IP cores, such as the AXIS ILA and AXISVIO cores
  • The different hard block debugging tools
  • Versal device debugging techniques for JTAG lowspeed debug and high-speed debug port (HSDP) debug
  • ChipScoPy APIs for hardware debugging

The workshop has been created to be accessible by a wide audience with standard technology requirements.

If you have not attended a Doulos workshop or webinar before, you can check your connection with the meeting service here »

 

Delivered across 2 half-day sessions the workshop contains the following topics:

  • Design Tool Flow
    Maps the various compute resources in the Versal architecture to
    the tools required and describes how to target them for final
    image assembly. 
  • Configuration and Debugging
    Describes the configuration and debug process for the Versal
    devices. Also covers the Versal device debug interfaces, such as
    the test access port (TAP) and debug access port (DAP)
    controller. 
  • Fabric Debug
    Explains the fabric debug features available in the Versal device
    and reviews the different debug IP cores supported for Versal
    devices, such as the AXI Debug Hub, AXIS ILA, and AXIS VIO.
  • Hard Block Debug
    Focuses on the debugging of Versal device hard blocks, such as
    the GTs, NoC, DDRMC, HBM, PCIe® block, PS, and AI Engines.
  • Overview of HSDP
    Describes the high-speed debug port (HSDP) in the Versal
    device. Also goes over the steps to use the SmartLynq+ module
    for high-speed debugging. 
  • ChipScoPy Overview
    Discusses the ChipScope hardware debug method and reviews
    how the ChipScoPy APIs are used for debugging the Versal
    device. 
  • System Integration and Validation Methodology
    Describes different simulation flows as well as timing and power
    closure techniques. Also explains how to improve system
    performance. 

Please come prepared to actively participate and engage directly with the workshop facilitator.

This workshop is delivered in 2 half-day sessions of interactive training comprising presentations with Q&A.

  • Each session duration is up to 5 hours including breaks 
  • Start times:
    • Europe and Asia Time Zones:
      0830 BST | 0930 CEST | 1300 India (IST)
    • Americas Time Zones:
      0830 PDT | 1030 CDT | 1130 EDT
  • There are no specific hardware requirements for this training please check your connection with GoToWebinar if you have not used it to attend a Doulos event before.

The workshops have kindly been sponsored by AMD, and are available to attend FREE OF CHARGE.

Usual value of this training is $990 / €840 

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Complete an enquiry form and a Doulos representative will get back to you.

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