The words FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device) are everywhere nowadays. Not just for systems that actually need to be re-programmed in the field, but for any application that can't justify the up-front expense of an ASIC.
Doulos works closely with our partners and leading technology vendors to train engineers in FPGA applications. This includes routine support for Altera, Lattice, Mircrosemi, and Xilinx technologies on our VHDL courses as well as dedicated FPGA training classes.
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This section of the website is dedicated to programmable logic devices - the 4 Ts... Tools, Technology, Tips, Tricks.
Organising a collection of tips like this can be tricky! So if you cannot find what you want, just use the Search box at the top right of the page. You'll find that information is linked from different places in the list below - for instance setting generics on parameterised designs using Xilinx ISE can be accessed from the Tools, Technology, or Tips links depending on whether you look for Xilinx ISE (a Tool), Xilinx (a technology) or setting parameters (a Tip).
One other note: although many of these examples use VHDL, they often apply equally well to Verilog - it's just that in our training experience, the majority of FPGA/CPLD users are using VHDL.
Detecting events that are shorter than your clock period. VHDL and Verilog code available.
Issues in large multiplexer structures.
Producing a nice clean input signal from a messy source. VHDL and Verilog code available.
A discussion of the issues and some suggestions for solutions. VHDL and Verilog code available.