Hardware engineers using VHDL often need to test RTL code using a testbench. Given an entity declaration writing a testbench skeleton is a standard text manipulation procedure. Each one may take five to ten minutes.
Every design unit in a project needs a testbench. Generating testbench skeletons automatically can save hours per project. However, a little Perl programming can reduce that time to seconds in future.
Below you'll find a Perl script to generate a skeleton testbench given an entity declaration. In fact, if an architecture is supplied then the Perl script will add in a Reset and Clock generator process (if the architecture uses a clock). Configuration declaration(s) are generated too.
Copy and paste your own declarations or use our sample code below. Then click the Generate VHDL Testbench button.