A design is described in VHDL using the concept of a design entity. A design entity is split into two parts, each of which is called a design unit in VHDL jargon. The entity declaration represents the external interface to the design entity. The architecture body represents the internal description of the design entity - its behaviour, its structure, or a mixture of both. Let's imagine we want to describe an and-or-invert (AOI) gate in VHDL. If we consider the AOI gate as a single chip package, it will have four input pins and one output pin; we need not concern ourselves with power and ground pins in modelling our AOI design.
-- VHDL code for AND-OR-INVERT gate library IEEE; use IEEE.STD_LOGIC_1164.all; entity AOI is port ( A, B, C, D: in STD_LOGIC; F : out STD_LOGIC ); end AOI; architecture V1 of AOI is begin F <= not ((A and B) or (C and D)); end V1; -- end of VHDL code
-- VHDL code for AND-OR-INVERT gate
Similar to many programming languages, VHDL supports comments. Comments are not part of the VHDL design, but allow the user to make notes referring to the VHDL code, usually as an aid to understanding it. Here the comment is a “header” that tells us that the VHDL describes an AOI gate. It is no more than an aide de memoire in this case. A VHDL compiler will ignore this line of VHDL. Two hyphens mark the start of a comment, which is ignored by the VHDL compiler. A comment can be on a separate line or at the end of a line of VHDL code, but in any case stops at the end of the line.
library IEEE; use IEEE.STD_LOGIC_1164.all;
Above the entity declaration is a library clause (library IEEE;) and a use clause (use IEEE.STD_LOGIC_1164.all;). This gives the entity AOI access to all the names declared within package STD_LOGIC_1164 in the library IEEE, and to data type STD_LOGIC in particular. More on data types later.
entity AOI is
The name of the design entity is just an arbitrary label invented by the user. It does not correspond to a name pre-defined in a VHDL component library. entity and is are VHDL keywords. This line defines the start of a new VHDL design unit definition. The library and use clauses, although written before the entity declaration, do not define the start of the VHDL description of a design unit, they are context clauses. We can think of an entity declaration as corresponding to a chip package.
port ( A, B, C, D: in STD_LOGIC; F : out STD_LOGIC );
The entity declaration includes the name of the entity (AOI in this example), and a set of port declarations. A port may correspond to a pin on an IC, an edge connector on a board, or any logical channel of communication with a block of hardware. Each port declaration includes the name of one or more ports ( e.g. A, B), the direction that information is allowed to flow through the ports (in, out or inout), and the data type of the ports (i.e. STD_LOGIC). In our example the port declarations correspond to the pins of our AOI chip.
The data type of a port defines the set of values that may flow through the port. The ports are of type STD_LOGIC, which is found in package STD_LOGIC_1164 in library IEEE. A package is a VHDL language construct where new data types may be defined, and the particular package STD_LOGIC_1164 is an IEEE standard for representing digital signals in VHDL. The concept of data type is borrowed by VHDL from the world of software. It allows the VHDL compiler to ensure that the design is at least reasonably robust before beginning simulation.
The entity declaration is terminated by the VHDL keyword end. Here we indulge in a little programming robustness by adding the name of the design entity after the end keyword. Including the name of the design entity is particularly relevant in large descriptions where the port list may extend over many screens (or pages); it is good to be reminded of the name of the design entity whose end we are looking at, lest we forget.
architecture V1 of AOI is
The name of the architecture body (V1) is just an arbitrary label invented by the user. It is possible to define several alternative architecture bodies for a single design entity, and the only purpose of the architecture name is to distinguish between these alternatives. architecture, of and is are VHDL keywords. Note that when we define an architecture, we have to tell the VHDL analyzer that the architecture V1 corresponds to the AOI design entity. You might think that it would be enough to specify the name of the architecture and that the architecture automatically corresponded to the previously declared entity, but I'm afraid VHDL doesn't work this way! In essence, we can think of the architecture as the die inside the chip package.
The VHDL keyword begin denotes the end of the architecture declarative region and the start of the architecture statement part. In this architecture, there is but one statement, and all the names referenced in this statement are in fact the ports of the design. Because all of the names used in the architecture statement part are declared in the entity declaration, the architecture declarative part is empty.
F <= not ((A and B) or (C and D));
The architecture contains a concurrent signal assignment, which describes the function of the design entity. The concurrent assignment executes whenever one of the four ports A, B, C or port D change value. That's it! That's all there is to describing the functionality of an AOI gate in VHDL. Some might regard the rest of the VHDL code as superfluous and level a charge of verbosity against VHDL. Of course, the remainder of the VHDL code is setting the context in which this functionality is defined.
The architecture is terminated by the VHDL keyword end. Once again, we reference the architecture name at the end of the architecture body for the same reason as we did with the entity. Usually, architecture bodies require sigificantly more code than entity declarations, hence repeating the name of the architecture is even more relevant.
-- end of VHDL code
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