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Arm Cortex-M3/M4 SoC Design
Arm® Cortex®-M3/M4 SoC Design is a 3-day class for engineers designing hardware based around the Arm Cortex-M3/M4 core. It includes an introduction to the Arm product range and supporting IP, programmer's model, instruction set architecture, AMBA on-chip bus architecture and Cortex-M3/M4 debug architecture. The class includes a number of worked examples developed by Arm to reinforce the lecture material.
Hardware design engineers who need to understand the issues involved when designing SoC's around the Arm Cortex-M3/M4 core.
Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of Arm is useful but not essential.
This class uses training materials developed by Arm®
An overview of the Cortex-M3 and Cortex-M4 processor cores that discusses the pipeline, memory map and other key features.
Detailing the processor pipeline and instruction execution.
Introduces the exception handling model for Architecture v7-M. Explains how to write software handlers and manage interrupts.
Outlines the main features of the Thumb instruction set. Provides a primer for those needing to interpret compiler output or write low level code.
Showing the differences between Cortex-M3 and Cortex-M4. Introducing DSP and SIMD instructions, Floating Point Unit and extended exception stack frame.
Explains the AMBA 3 AHB-Lite Bus protocol.
Explains the AMBA APB Bus protocol.
Detailed discussion of the memory system bus interfaces at the processor and integration levels.
Explains the reset and clocking requirements and operation of sleep modes. Introduces the Wake-up Interrupt Controller.
Introduces the Memory Protection Unit. Explains memory types and attributes, and how to configure memory protection regions.
Introduces the built-in System Timer function and explains the calibration function.
Introduces CoreSight and the DAP components and ROM Table. Overview of Debug and Trace capabilities and standard debug connectors.
Detailed view of debug capabilities, DAP components, and Flash Patch & Breakpoint Unit.
Explanation of instruction trace methodology. Detailed view of instrumentation trace and data watchpoint and trace units and trace port. Discussion of trace clocking.
Brief overview of Cortex-M3 example system and Cortex-M4 Integration Kit. Introduction to ‘tarmac’ and to multi-processor integration.
Details of RTL configuration. Overview of design flow steps and introduction to Reference Methodologies.
Overview of CMSDK components and example systems.
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