This course covers software aspects of designing with an Arm® Cortex®-A35/A53/A57/A72 MPCore based device, highlighting the core architecture details and the programmer's model. Topics include the Arm AArch64 exceptions model, details of the available caching schemes and coherency management, memory management and the Arm memory model. Additionally the sections on the v8 architecture instruction set and steps involved in initializing an MPCore system deliver the essential knowledge required for programming and debugging a Cortex-A35/A53/A57/A7 MPCore processor.
The learning is reinforced with unique Lab exercises using the Armv8-A 64 bit QEMU virtual platform. The laboratories run inside a self contained virtual machine environment. This allows the student to experience a real-life and project ready development environment without the complexity of installing complex software prior to the class. This virtual machine is for the student to keep after the training class, allowing you to further experiment with embedded software development once the class has come to its completion.
Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required.
C programming for Embedded Systems training is also available from Doulos.
A carefully crafted combination of content from Arm and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes fully indexed course notes creating a complete reference manual.
Privilege levels • AArch64 registers • A64 Instruction Set • AArch64 Exception Model • AArch64 Memory Model
Core pipelines • Configuration options • Branch prediction • Cache overview • Data cache coherency • Memory management • Micro-architectural features • Interrupts and bus interfaces • Debug and timers • Big-little
Registers • Loads and stores • Data processing and control flow • Scalar floating-point and SIMD
Synchronization in ARMv8-A • Local and Global Exclusive Monitors
The AArch64 exception model • Interrupts • Synchronous exceptions • SError • exceptions • Exceptions in EL2 and EL3
Booting an ARMv8-A processor in AArch64 • Booting multi-core and multi-processor systems • Real-world booting
General Cache Information • Cache Attributes • Cache Maintenance Operations • Cache Discovery
Memory Management theory • Stage 1 Translations at EL1/0 • Translations at EL2 / EL3 • TLB maintenance
Types • Attributes • Alignment and endianness • Tagged pointers
Data barriers • Instruction barriers
Context Switching • Modifying Translation Tables • Privilege Escalation Protections • Timers
Why do we need a Secure environment? • Software stack • System architecture
Introduction to coherency • Coherency details - multi-core processors • Coherency details - multi-processor systems
What is virtualization? • ARM virtualization support • Memory management • Exception handling
ARM core power modes • Power control • ARM multi-core processor power modes • Power state coordination
Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues
Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries
Introduction to Debug • Types of Debug • Debug Facilities • External Debug • Self-hosted Debug • CoreSight • Debug Features • Trace
Introduction • Performance Monitoring Hardware: PMU • Cycle Accurate Trace: Trace • Macrocells • Streamline Performance Analysis
Interrupt Controller • System MMU • TrustZone Address Space Controller • Generic Timer
The learning is reinforced with unique Lab Exercises using an Armv8-A 64 bit instruction set simulator and covering assembly programming, exception handling and setting up the caches and MMU.
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