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Introduction to SystemVerilog Self-Paced

Intermediate Level -  Online Self-Paced - Total Duration 3 days

SystemVerilog (IEEE 1800™), the successor to the Verilog® hardware description language, has become the dominant language standard for functional verification. SystemVerilog significantly enhances the capabilities of Verilog in a number of areas, offering productivity improvements for RTL designers, assertions, and constrained random stimulus generation for verification engineers. 

Introduction to SystemVerilog  teaches the basics of the SystemVerilog language that are useful for both design and directed test verification.

From an overview of the language and its evolution, the training provides a foundation for learning SystemVerilog from basic principles, to the synthesizable RTL language features.

This training is only available via the Doulos Thinkific Learning Portal. Please contact your local Doulos team to discuss your training needs and how to access the course. 

  • Design engineers who wish to make full use of SystemVerilog's class-based verification capabilities for test bench development as well as learning SystemVerilog for RTL design.
  • Verification engineers aiming to deploy coverage driven verification approaches for the first time using SystemVerilog
  • Verification engineers wishing to migrate to SystemVerilog class-based verification from other established verification languages and test bench automation techniques
  • Engineers and managers who wish to evaluate the full range of SystemVerilog's capabilities for design and verification
  • EDA support engineers who wish to gain a comprehensive understanding of how their customers' engineering teams can most productively use SystemVerilog in both design and verification domains
  • The training lays the foundation for learning the SystemVerilog language for design and for verification.

  • The course teaches the synthesizable RTL language features of SystemVerilog. For hardware designers, this assumes an understanding of RTL synthesis with Verilog or VHDL. For verification engineers, this provides some familiarity with the RTL constructs as used by hardware designers.

A good working knowledge of Verilog is essential:

  • For engineers with no HDL knowledge or experience the Doulos Comprehensive Verilog course, or equivalent, is an essential precursor.
  • For engineers with no Verilog knowledge, but with working experience of VHDL, Doulos offer a Fast Track Verilog for VHDL Users class in a format tailored to equip delegates with the necessary foundation for SystemVerilog.
  • For onsite courses, precursor training in Verilog can be tailored to the specific team profile and combined with appropriate SystemVerilog modules to fully address team needs (see Modular SystemVerilog).

If you require any of these precursor training options please contact the Doulos team to discuss what will best suit your needs, or complete an online enquiry.

Doulos class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:

  • Fully indexed class notes creating a complete reference manual
  • Workbook full of practical examples and solutions to help you apply your knowledge
  • Doulos SystemVerilog Golden Reference Guide e-book for language, syntax, semantics and tips

If you would prefer a paperback version of your Doulos Golden Reference Guide, this can be purchased from the Doulos online shop.



What is SystemVerilog? • Language Evolution • SystemVerilog versus Verilog • Reg, Logic, and Bit • Variables, Wires, and Ports • SystemVerilog Language Features • Caveats • The UVM Family Tree • Books and Resources

Programming Language Features

C-Like Language Features • Static vs Automatic Variables • Static vs Automatic Tasks • ++, --, and Assignment Operators • Labeling • Time Units • Do While Loop • Enhanced Tasks and Functions • Task and Function Arguments • Void Functions • Argument and Return Types • Type string • $sformatf

Basic Data Types

4-state and 2-state Types • Caveats with Signed Types • Initial Values • Every variable and wire has a well-defined initial value • Enumerations • Type-Checking of Enumerations • struct • typedef struct • Packed Struct • Packed and Unpacked Arrays • Indexing Multidimensional Arrays • Packages • Packages and Ports


Modelling a Bus • APB with Master and Single Slave • Modelling APB using Ports • Simple Interface = Bundle of wires/vars • Using an Interface • Accessing Interface Members • Modports • Modport Directions • Connecting Interfaces with Modports • Generic Interface Ports • Ports and Parameters to Interfaces

RTL Process

SystemVerilog and RTL synthesis • Register Transfer Level • Combinational Logic • Clocked Processes • always_comb, always_latch, always_ff • Synthesis-Friendly If / Case • priority case • unique if • unique case • Wild Equality Operators • case inside • inside Operator

RTL Types

Synthesizable Data Types • Enums for Finite State Machines • Base Types and Values • Rules for Overriding the Enum Values • Packed Struct (Review) • Packed Union • Multidimensional Arrays • Odds and Ends • Nets, Ports and Data Types • Types and Packages • Type Parameters • Synthesis of Interfaces (Review) • Synthesis Results (Review) • Multiple Drivers on a Bus • How to Differentiate Connections? • Modport Expressions • Modport Expressions with Generate

Clocking Blocks and Timing

Input and Output Skew • Creating a Clocking Block • Testbench and Clocking Block • Cycle Delays and Clocking • Input and Output Skew Syntax Summary • Scheduler Regions • Stimulus and Response • Signal Aliasing • Multiple Clocking Blocks • Driving a Net • Clocking Blocks in Interfaces • Clocking Blocks versus Program

Arrays and Queues

Dynamic Arrays • Queues • Working with Queues • Queue Methods • Associative Arrays • Associative Array Methods • Foreach

Bus-Functional Modeling

Simple Module-Based BFM • Testbench using BFM • Separate Test from Test Harness • Task/Function in Interface • APB Interface With Tasks • An APB Test


Testbench Automation • Random Numbers in SystemVerilog • std::randomize • Seeding and Random Stability • Saving & Restoring Seeds • Random Sequence of Valid Actions • Randcase • Randsequence • More Randsequence Features


Test bench Automation • Functional Coverage • Covergroup Syntax • Coverage Bins • Cross Coverage

Other Language Features

$root and $unit • Enumeration Methods • Arrays for Multidimensional Structures • Initializing an Unpacked Array • Replication in an Assignment Pattern • Packed Arrays and Structures • Pass-by-Copy • Pass-by-Reference • const ref • Array Querying Functions (1) • Array Querying Functions (2) • $bits • Bit-stream Casting • Array Manipulation Methods • Array Locator Methods • Array Ordering Methods • Array Reduction Methods

The Direct Programming Interface

DPI Simulation Flow • Command-line Switches • Importing a C Function • Changing the Imported Function Name • Mapping Data Types of Arguments • Exporting a Function to C • Sandwiches and Transparency • Importing and Exporting Tasks • Scalar Bit and Logic Arguments • Packed Arrays • Decoding the Canonical Representation • String Arguments • Open Array Arguments • Task Return Values • Task Disable Flow • Pure and Context

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