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VHDL-AMS Adopter Class is a comprehensive 4 day course covering the extension to VHDL for analogue and mixed-signal modelling, as well as the underpinning VHDL knowledge required. It includes VHDL-AMS language features, with examples of electronic circuits and systems, and new constructs are explained with reference to circuit simulation algorithms.
The first 2 days of the class examine the VHDL language essentials: Coding for register transfer level writing test benches, using VHDL tools and the VHDL design flow. Engineers already proficient in VHDL can omit the 'Introduction to VHDL' module and attend just the last 2 days.
The course is split between interactive classroom-style lectures and practical hands-on exercises using a commercial simulation tool. The workshops are carefully designed to reinforce the material presented and illustrate the scope of the language with interesting exercises.
Engineers who wish to extend their knowledge of VHDL to the modeling of analogue and mixed-signal electronic circuits.
Knowledge of SPICE or other analogue simulation tools would be advantageous but is not essential. Some basic circuit theory will be used and a familiarity with the general concepts (such as Kirchhoff's laws) would be helpful.
Doulos training materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. Class fees include:
If you would prefer a paperback version of your Doulos Golden Reference Guide, this can be purchased from the Doulos online shop.
The scope and application of VHDL • Design flow • Benefits • Tool and Technology independence • The VHDL world
The basic VHDL language constructs
The proper organisation and use of VHDL source files and libraries • The compilation procedure
The process statement and its consequences for simulation and modeling
If, case and loop statements w combinational logic and transparent latches • generating test vectors
Defining new data types • modeling tri-state busses w manipulating vectors, using operators • conversion functions • standard packages
Making best use of integers and arrays • modelling memories
Parameterising designs for re-use • concurrent coding styles • using assertions to report errors
Procedures and functions in test benches and RTL code • understanding packages • operator overloading
Review of VHDL 1076-1999 • Maths package 1076.2 • Signal flow modelling in VHDL • 1076.1 (VHDL-AMS) Background
Definition of a nature • Terminal nodes • Free quantities • across and through quantities • Electrical package
Simultaneous statements • Implicit quantities • Solvability • Simultaneous if and case statements • Examples: Resistor, capacitor, diode
Terminal and quantity ports • Component instantiation • Signal flow modelling
Sequential programming constructs • Equivalent simultaneous statements • Equivalent functions • Examples: MOSFET, Opamp
Simulation cycle • Initialisation • Break statements • Time step control • Frequency and Noise domain modelling
Mixing concurrent and simultaneous constructs • Events • Examples: ADC, DAC
Limitations • Future of VHDL • Object-oriented VHDL • Future of VHDL-AMS
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