In addition to Clock and IO constraints, multicycle path, false path and other timing exceptions constraints are also discussed.
- Spartan-6 users who want to migrate their existing design to the latest FPGA technology and are new to Vivado ML.
- FPGA designers who want to refresh their knowledge of XDC timing constraints. In addition to Clock and IO constraints, multicycle path, false path and other timing exceptions constraints are also discussed.
The emphasis of this workshop is on:
- Comparing Spartan-6 with 7 Series Architectures
- Migration flow
- Introducing Vivado ML
- Introducing the IP Flow
- Creating XDC timing constraints
- Spartan-6 to Spartan-7 Architecture Migration
Guidance on migrating from Spartan-6 to other families – The architectural differences between the Spartan-6 and Spartan-7/Artix®-7 – Some available resources to help guide people through the transition from ISE to Vivado
- Introduction to Vivado ML Editions Tool FLow
Describes the various design flows in the Vivado Design Suite - Explains how the Vivado Tools flow is different from ISE tool flow - Identifies and describes the supported use models in the Vivado Design Suite - What is a Netlist - How to create a project in Vivado ML and explain the different flow options - Briefly talk about IP Integrator and Vitis HLS
- Vivado ML Project Mode
Describes the project mode use model in the Vivado ML – Describes the structure and files of a project – How to create a simple Vivado ML project in project mode
- Synthesis and Implementation
Describes the synthesis and implementation processes in the Vivado IDE and the reports that are available after the process
- Vivado IP Flow
Describes the Vivado IP Flow , how to access IP from the IP catalog and describe the output files and synthesis flow
- Introduction to XDC Clock Constraints
Provides a brief introduction to clock constraint and their properties in the Vivado Design Suite
- Generated Clocks and Clock Groups
Describes generated clocks in the Vivado ML Editions and introduces the application of clock group constraints that are used by the Vivado timing engine to resolve timing issues
- IO Constraints and Virtual Clocks
Introduces how I/O timing constraints are made with the Vivado IDE for single data rate applications
- Setup and Hold Timing Analysis
Covers the setup and hold timing analysis.
- Timing Constraints Wizard
Explains use of the Timing Constraints Wizard to create timing constraints and validate their completion
- UltraFast Design Methodology Design Creation
Introduces the design creation guidelines for the UltraFast™ Design Methodology
- Introduction to Timing Exceptions
Introduces the application of multicycle paths, false paths, and max/min delay exception timing constraints
- Timing Constraints Priority
Discusses the XDC precedence for timing exception constraints priority
This workshop is delivered in one 7 hour session of interactive training comprising presentations with Q&A.
- Americas workshop start time
- September 29th:
0800 PDT | 1000 CDT | 1100 EDT
- EurAsia workshop start time
- September 30th:
0800 BST | 0900 CEST | 1230 IST
- There will be regular breaks throughout the training including one extended break
- There are no specific hardware requirements for this workshop, please check your connection with GoToWebinar here if you have not used it to attend a Doulos event before.
FREE OF CHARGE sponsored by Xilinx
Register for this FREE workshop using a link below:
Americas Timezones - Sept 29 2022 - REGISTER NOW >
EurAsia Timezones - Sept 30 2022 - REGISTER NOW >