The Doulos Assertion-Based Verification with PSL provides in-depth tuition in the use of Accellera’s Property Specification Language (PSL) in the context of an assertion-based verification methodology for digital electronic design.
Assertions benefit design and verification by removing ambiguity from specifications, finding bugs sooner and allowing fewer bugs through to production. The Doulos course enables successful adoption of assertions into projects by delivering an in-depth understanding of the language and a verification methodology to exploit it. The application of assertions to real project situations is demonstrated throughout, and is supported by extensive hands-on experience gained within the workshop sessions.
The Doulos Assertion-Based Verification course is presented from a vendor independent perspective but with workshops using a choice of leading HDL simulators.
The ability to read and understand simple examples of VHDL or Verilog® code is essential, and experience running HDL simulations is recommended. The ability to write original VHDL or Verilog code is not required.
Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Course fees include:
How properties fit with verification • Simulation • Code coverage • Constrained random test generation • Functional coverage • Hardware verification languages • Assertion languages • Accellera standards • Formal verification • Property checking • Assertion-based verification
Properties • Assertions • Simulation checkers • State space exploration • Assumptions and restrictions in static property checking • Verification coverage and corner cases • Assume-guarantee methodology • Assertion coverage • Automatic properties
Who writes properties? • Properties and the specification • Properties for the design and verification engineers • Observability and bug localisation • Property re-use • Debugging properties • Assertion density • Impact on documentation standards and review
The boolean, temporal, verification and modelling layers • VHDL and Verilog flavours • Clocks • Verification directives • Verification units • Named properties • Safety and liveness properties • Simulation issues and the simple subset • The practicalities of using PSL with an HDL simulator
Learning common temporal operators by example • always • never • next • eventually! • rose(), fell() and prev() • until • before • abort • Operator precedence • Practising the use of these operators to write common properties
Sequences and Sequential Extended Regular Expressions • Sequence implication • Repetition operators • Parameterised sequences • Sequence composition operators • Practising the use of the typical form for a PSL property
Functional coverage • Assessing coverage • Refining assertions • Transaction based assertions
Reusable assertions • Test modules • AMBA example
The Foundation Language and Optional Branching Extensions • LTL and CTL operators • Further sequence operators • Ranges • Non-consecutive and goto repetition • Endpoints • next_event • whilenot • within • forall • Macros • The Verilog modelling layer • (These features are not necessarily supported by all current verification tools)
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