Global training solutions for engineers creating the world's electronics products

The Latest Methodologies for Design Verification

Duration 5 days

This course is delivered in co-operation with Doulos training partner and verification specialists Test and Verification Solutions.

The course introduces participants to the state-of-the-art techniques and methods in dynamic and formal design verification and how these fit into the modern verification process. Participants are equipped with foundation and advanced knowledge in design verification and have the opportunity to develop practical skills in dedicated lab exercises.

The course is flexible in terms of the design or verification language and EDA tools to be used in the practical lab exercises. It can be delivered as a 3 day course focused on methodologies for dynamic design verification followed by a 2 day course on formal verification, in particular model checking. The course can also be delivered in a bespoke sequence interleaving dynamic with formal design verification training modules and labs or shortened to 4 days depending on your preferences. Please contact Doulos to discuss your requirements.

Hands-on lab exercises are an integral part of the training. Lab exercises are designed to allow participants to practice the material presented and discussed in the training modules. Labs comprise approximately 33% of the class time.

Who should attend?
  • Design and Verification Engineers who would like to improve their knowledge of the latest techniques and methodologies for dynamic and formal design verification and who would like to update their understanding of how these fit into a state-of-the-art design verification process.
  • Engineering Managers who would like to become more familiar with the design verification process and the options available in terms of methodology and tool support for their teams.
  • Companies striving to move to the latest verification techniques and strategies.
What will you learn?
  • You will gain a thorough understanding of the Design Verification process, its importance, fundamental principles, terminology, complexities and limitations.
  • You will learn how to develop and maintain a verification plan, set verification goals and select verification methods, techniques and tools to achieve these.
  • You will gain knowledge of how to use state-of-the-art dynamic verification techniques and methods including constrained pseudo-random test generation, coverage collection and analysis, advanced checking, assertion-based verification and hardware acceleration.
  • You will gain knowledge and understanding of formal verification techniques, especially formal property checking, including how to use a property checking tool and how formal verification can complement traditional dynamic design verification techniques.
  • You will learn how to carry out functional design verification at block and at system level using dynamic and formal methods as well as combined techniques and advanced verification methodologies.
  • No prior knowledge of verification is required.
  • Familiarity with the digital design process and basic understanding of computer architecture is assumed.
  • Familiarity with the basic functionality of the EDA tools used in the labs is assumed.
  • Basic programming skills are helpful for the lab exercises.
Course materials
  • Course fees include fully indexed course notes providing you with a complete reference manual.
  • A Workbook with all lab exercises and example solutions is included.
  • The source code for the lab exercises will also be provided.
Structure and content


Motivation • Cost of Bugs • Terminology • The Design Process • The Verification Process • Observability • Controllability • Verification Levels

Verification Planning

Importance of Planning • Specifications • Feature Extraction • Identifying Corner Cases • Targets and Metrics • Unit and System-Level Verification Planning

Directed Testing

Verification Tools and Languages • Basics of Testbenches • Driving and Checking • Limitations

When is verification done?

Sign-off Criteria • Comprehensive Code Coverage • Functional Coverage • Combining Coverage Models • The Coverage Closure Challenge • Regressions • Verification Management

Constrained Random Generation

Motivation • Coverage with a focus on Functional Coverage • Testbench Automation • Modern Testbench Structure • Transactors • Coverage-driven Verification

Advanced Checking

How to predict expected results • Advanced Checkers • Reference Models • Self-checking Testbenches • Monitors • Scoreboards • Coherency

Assertion-Based Verification

Terminology • Use • Temporal Properties • Property Formalization • Simulation with Assertions • Observability • Assertion Coverage • Property Re-use

System-Level Verification

Architecture of the top-level Testbench • Top-Level Testing • Controllability and Observability • Advanced Constrained Random Techniques • Configurations • Warm Loading • System-Level Properties and Assertions • System-Level Debug • Coverage above Unit Level • Power-Aware Verification • Accelleration • Validation • Performance Verification • Quality of Service

Verification Flow

Specification • Plan • Verification Environment • Debug • Regression • Escape Analysis • Re-use • Advanced Verification Methodologies • Verification Review

Foundations of Formal Verification

Motivation • Terminology • Formal Property Checking • Developing Properties • Safety, Liveness and Invariant Properties • Environment and Assumptions • Interpreting the Outcome of Formal Property Checking • Coverage • Benefits and Strengths of Formal Verification

Advanced Formal Verification

Bug Hunting • Bug Absence • Bug Analysis • Checking Bug Fixes • Coverage Closure • X-Propagation • Advanced Property Specification and Capture • Strategies for Coping with Complexity • Bounded Proof • Bug Avoidance • Finding Invariants • Property Re-use and libraries

Looking for team-based training, or other locations?

Complete an enquiry form and a Doulos representative will get back to you.

Enquiry FormPrice on request