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Designing with the Xilinx 7 Series Families ONLINE

Training Duration: 4 sessions (4 hours per session)


PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.

It covers the same scope and content as a scheduled in person class and delivers comparable learning outcomes.

Course Description

Are you interested in learning how to effectively utilize 7 series architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course and focuses on understanding, as well as how to properly design for, the primary resources found in this popular device family.


Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express® technology, analog to digital converters and gigabit transceivers) are also introduced.


This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA. A combination of modules and labs allow for practical hands-on application of the principles taught.
Who Should Attend?
FPGA designers looking to effectively utilize the architectural resources of Xilinx 7 Series devices
Software Tools

Vivado® HL Design or System Edition 2017.3

  • Architcture: Artix™-7, Spartan®-7,  Kintex™-7 and Virtex® FPGAs*
  • Demo Board: None
* This course focuses on the 7 series FPGA architectures. Please contact Doulos for the specifics of the in-class lab board or other customizations.
Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the 7 series FPGAs
  • Specify the CLB resources and the available slice configurations for the 7 series FPGAs
  • Define the block RAM, FIFO and DSP resources available for the 7 series FPGAs
  • Properly design for the I/O block and SERDES resources
  • Identify the MMCM, PLL and clock routing resources included with these families
  • Identify the hard resources available for implementing high performance DDR3 physical layer interfaces
  • Describe the additional dedicated hardware for all the 7 series family members
  • Properly code your HDL to get the most out of the 7 series FPGAs
Course Outline

Sessions 1 & 2

  • Introduction to the 7 Series Architecture {Lecture}
  • CLB Resources {Lecture, Lab}
  • Slice Flip-Flops {Lecture}
  • HDL Coding Techniques {Lecture, Lab}
  • Clock Structure and Layout {Lecture}
  • Clock Buffers {Lecture}
  • Clock Management {Lecture}
  • Clock Routing {Lecture}
  • Using Clock Resources {Lecture, Lab}
  • Dedicated Hardware Resources {Lecture}


Sessions 3 & 4

  • Block RAM Memory Resources {Lecture, Lab}
  • FIFO Memory Resources {Lecture}
  • Memory Controllers {Lecture}
  • DSP Resources {Lecture, Lab}
  • I/O Resources Overview {Lecture}
  • I/O Electrical Resources {Lecture}
  • I/O Logical Resources {Lecture, Lab}
  • Transceivers {Lecture}

Looking for team-based training, or other locations?

Complete an enquiry form and a Doulos representative will get back to you.

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