- Counting Short Pulses
Detecting events that are shorter than your clock period. VHDL and Verilog code available.
- Implementing Large Multiplexers
Issues in large multiplexer structures.
- Cleaning Dirty Signals
Producing a nice clean input signal from a messy source. VHDL and Verilog code available.
- Synchronisation and Edge-Detection
A discussion of the issues and some suggestions for solutions. VHDL and Verilog code available.