1 hour session (All Time Zones)
Presenter: Brian Jensen
Digital designers have been talking about design reuse for 30 years or so. Given that writing the testbench can be as much, if not more, effort than creating the design, testbench reuse is just as important, if not more. A structured testbench enables a powerful testbench to be designed that can much more easily be reused across block- and chip-level testing, across projects and across products.
This webinar introduces some modern verification concepts and shows how you can create a structured testbench in VHDL by presenting a VHDL testbench methodology.
Brian Jensen , Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.
Attendance is free of charge
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