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Company Registration Information

Die Doulos GmbH ist eine hundertprozentige Tochtergesellschaft der Doulos Ltd.

Doulos Ltd ist ein Privatunternehmen, das im Vereinigten Königreich (UK) eingetragen ist. Neben seinem Hauptsitz in England unterhält Doulos Niederlassungen bzw. Betriebe in anderen Ländern wie Deutschland und den USA.

Doulos Ltd ist in England und Wales unter der Firmennummer 03723454 eingetragen. Der eingetragene Firmensitz ist: 4 Brackley Close, Bournemouth International Airport, Christchurch, BH23 6SE, UK.

Geschäftsführer: Thomas Winkler

Firmensitz Munich
Doulos GmbH
Konrad-Zuse-Platz 8

81829 München

Deutschland/Germany

Court Registergericht München: HRB 259317

MwSt Nummer: DE 226 222 648
Steuernummer: 25/279/02493

Upcoming Live Webinars

Extending a Yocto BSP using Layers

Wednesday February 26 2025

1 hour session (All Time Zones)

We will investigate how the Yocto build environment provides the initial components to successfully boot a Linux system and how it can be modified to manage challenging requirements in your projects.

Rapid Creation of Edge AI Solutions on an FPGA

Friday February 28 2025

1 hour session (All Time Zones)

This webinar will explore ideas on identifying and deploying trained AI models on FPGAs and look at contemporary software tools and APIs which help in putting together an FPGA-based Edge AI solution.

Python in One Hour

Friday March 14 2025

1 hour session (All Time Zones)

Learn the basics of the Python language and what makes it different from other programming languages, as well as discover the richness of the Python libraries and add-on packages.

Accelerating Formal Verification Using Non-Determinism

Wednesday March 26 2025

1 hour session (All Time Zones)

This webinar will explain what non-determinism is, how it's used, and show lots of examples so you can take advantage of non-determinism to accelerate the verification of your designs.

A Guide to Productivity in Vivado using SystemVerilog

Friday March 28 2025

1 hour session (All Time Zones)

We will explore the features of SystemVerilog that are useful for RTL synthesis using the Vivado™ Design Suite from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.