How much SystemVerilog training do you need?
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SystemVerilog (IEEE 1800™), the successor to the Verilog® hardware description language, has become the dominant language standard for functional verification. SystemVerilog significantly enhances the capabilities of Verilog in a number of areas, offering productivity improvements for RTL designers, assertions, and constrained random stimulus generation for verification engineers.
SystemVerilog for Designers ONLINE prepares the engineer for practical project readiness for FPGA or ASIC design, including RTL synthesis, block-level test benches, and FPGA design flows. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects. While the emphasis is on the practical SystemVerilog-to-hardware flow for FPGA devices, this training course also provides the essential foundation needed by ASIC and FPGA designers wishing to go on to use the advanced features of SystemVerilog for functional verification.
SystemVerilog for Designers ONLINE is suitable for delegates with existing experience of Verilog or VHDL as well as for those who are learning SystemVerilog as their first hardware description language. For verification teams who are looking to use the class-based features of SystemVerilog for constrained random functional verification, Doulos provides Modular SystemVerilog for in-house training options.
Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.
The course includes specific lab support for tool sets from the leading FPGA vendors including the vendor's native simulation and place-and-route tools.
What you will learn
- The SystemVerilog language concepts and constructs essential for FPGA and ASIC design
- How to write SystemVerilog for effective RTL synthesis
- How to write simple and efficient module-based (as opposed to class-based) SystemVerilog test benches
- The tool flow from SystemVerilog through simulation, synthesis and FPGA place-and-route
- How to write high quality SystemVerilog code that reflects best practice in the industry
- How to write re-usable, parameterisable SystemVerilog code by exploiting parameters
Who should attend?
- Digital hardware design engineers who wish to learn how to use SystemVerilog for FPGA or ASIC hardware design at the register-transfer level (RTL) and for block-level verification
- Engineers and managers who wish to evaluate SystemVerilog for ASIC or FPGA design and block-level verification
- EDA support engineers who wish to understand how their customers' design teams can most productively use SystemVerilog
Prerequisites
- Delegates should have a good working knowledge of digital hardware design, or have attended Essential Digital Design Techniques (or equivalent)
- Some previous experience of RTL design using Verilog or VHDL is desirable, but not required
Training materials
Doulos class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:
- Fully indexed class notes creating a complete reference manual
- Workbook full of practical examples and solutions to help you apply your knowledge
- Doulos SystemVerilog Golden Reference Guide for language, syntax, semantics and tips
Structure and content
Introduction
The scope and application of SystemVerilog • Design and tool flow • FPGAs • Introduction to synthesis and synchronous design • SystemVerilog resources
Modules
Modules • Ports • Continuous assignments • Comments • Names • Design hierarchy • Module instantiation • Port connection shorthand • Test benches • Simple procedures
Numbers and formatting
Numbers • 2-valued & 4-valued logic • Vectors • Bit and part select • System calls • Output formatting • Time units • Strings • Always blocks • Ending simulation
Always blocks and Synthesis
Overview of RTL Synthesis • Event controls • if • begin & end • Combinational logic • always_comb • Synthesis of flip-flops and latches • Avoiding race hazards • Blocking & non-blocking assignments • Dealing with the scheduler and with clock skew • always_ff •Synchronous & asynchronous resets • Clock enables • Incomplete assignment and latches • Conditional operator •
Procedural Statements
case • casez & casex • unique & priority • for • repeat • while • do • forever • break • continue • Labels • local variables
Operators and Names
Bitwise, logical, reduction, and equality operators • Concatenation • Replication • Shift operators • Hierarchical names
Finite State Machines
State machines architecture • Coding styles for state machines • enum • State encoding • Unreachable states and input hazards
Types and Packages
Integer types • vector arithmetic • signed & unsigned values • struct • packed • typedef • packed & unpacked arrays • modeling RAM • nets, ports & data types • package • using • Scope resolution
Randomization and Coverage
Constrained Random Verification • Random Numbers in SystemVerilog • std::randomize • Constraint Syntax •Functional Coverage • Covergroup Syntax • Coverage Bins • Cross Coverage
File Organization and Parameterized Modules
Compilation units • Compiler directives • include • Macros • Conditional compilation • parameter • localparam • Parameter overriding • Parameterized modules • generate
Tasks and Functions
task • function • Argument passing • return • local declarations • automatic
Interfaces
Simple Interface • Package versus Interface • Instantiating an Interface • Accessing Interface Members • Ports and Parameters on Interfaces • Pin-Level Interface • Modports • Generic Interface Ports • Task/Function in Interface • Calling Task through Interface Port
SystemVerilog Assertions
What are Properties? • Property versus Assertion • Immediate and Concurrent Assertions • Immediate Assertions • Assertion Failure Severity • Concurrent Assertions • Temporal Behaviour • Clocks and Default Clocks • Holds and Implication • Concatenation and Repetition • Simulation of Assertions
| Course Dates: |
| June 10th, 2019 |
ONLINE Americas |
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| September 2nd, 2019 |
ONLINE EurAsia |
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| October 7th, 2019 |
ONLINE Americas |
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| indicates CONFIRMED TO RUN courses. |
