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Friday February 28 2025
1 hour session (All Time Zones)
This webinar will explore ideas on identifying and deploying trained AI models on FPGAs and look at contemporary software tools and APIs which help in putting together an FPGA-based Edge AI solution.
Friday March 28 2025
1 hour session (All Time Zones)
We will explore the features of SystemVerilog that are useful for RTL synthesis using the Vivado™ Design Suite from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.