Free Online Training Events
Free Technical Resources
Classes are normally run in training room LC5 between 9am and 5pm
Please use visitor car parking in front of Building 4 and register with security at least 10 minutes before the course start time.
For your convenience here is a list (in no particular order) of hotels in the vicinity. Please don't forget to request the Xilinx rate at the time of booking.
Friday February 28 2025
1 hour session (All Time Zones)
This webinar will explore ideas on identifying and deploying trained AI models on FPGAs and look at contemporary software tools and APIs which help in putting together an FPGA-based Edge AI solution.
Friday March 28 2025
1 hour session (All Time Zones)
We will explore the features of SystemVerilog that are useful for RTL synthesis using the Vivado™ Design Suite from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.