Here are a few examples of Tcl and Tcl/Tk scripts that we've found useful in our own simulation and synthesis work. Of course they probably won't exactly meet your needs, but we hope they will provide you with some starting points for your own scripting efforts.
Go back to the Tcl KnowHow page
Regular Expression Visualiser Go!
Updated version 1.3 now available!
Interactive GUI tool to help you understand, develop and debug Tcl Regular Expressions.
Tk Buttons for EDA Tools Go!
Add buttons for frequently used commands to any Tcl based EDA tool.
Tcl/Tk Constellation Plot Display for ModelSim™ Go!
Adds a new polar (constellation) display to ModelSim's waveform viewer, so that you can interactively observe the relationship between two multi-bit numeric values - typically representing the in-phase and quadrature components of a digitised signal. Shows how to add new GUI features to ModelSim, and how to make your own Tcl code interact effectively with the tool's own GUI.
Find the driver of any net in Synopsys Design CompilerTM Go!
This text-only Tcl script works within Synopsys Design Compiler. Given the name of any port, pin or net, the script will look around the design hierarchy and report the hierarchical name of the gate that drives that signal. Shows a number of useful tricks for exploring the DC design database.
Fast VHDL compile script for ModelSimTMSE simulator Go!
This script clearly demonstrates why you should improve your productivity with scripting. This script saves hours of working the ModelSim GUI to recompile and resimulate VHDL/Verilog code during development. It is really easy to use and will save you lots of time starting right now with your current VHDL/Verilog design or verification work.
