In the last article, we looked at describing hardware conceptually using processes. What kind of hardware can we describe? What are the limitations? What kinds of VHDL statement can be used in processes to describe hardware? Well, we have already seen the use of an if statement to describe a multiplexer, so let's look at the if statement in a bit more detail...
process (sensitivity-list) -- invalid VHDL code! -- process declarative region begin -- statements end process;
The code snippet above outlines a way to describe combinational logic using processes. To model a multiplexer, an if statement was used to describe the functionality. In addition, all of the inputs to the multiplexer were specified in the sensitivity list.
signal sel, a, b : std_logic;
process (sel, a, b)
begin
if sel = '1' then
f <= a;
else
f <= b;
end if;
end process;
Sensitivity list
It is a fundamental rule of VHDL that only signals (which includes input and buffer ports) must appear in the sensitivity list.
Combinational logic
It transpires that in order to create VHDL code that can be input to a synthesis tool for the synthesis of combinational logic, the requirement for all inputs to the hardware to appear in the sensitivity list is a golden rule.
Golden Rule 1:
To synthesize combinational logic using a process, all inputs to the design must appear in the sensitivity list.
Altogether there are 3 golden rules for synthesizing combinational logic, we will address each of these golden rules over the next couple of articles in this tutorial.
If
The if statement in VHDL is a sequential statement that conditionally executes other sequential statements, depending upon the value of some condition. An if statement may optionally contain an else part, executed if the condition is false. Although the else part is optional, for the time being, we will code up if statements with a corresponding else rather than simple if statements. To incorporate more than one sequential statement in an if statement, simply list the statements one after the other, there are no special bracketing rules in VHDL as there are in some programming languages,
signal f, g : std_logic; -- a new signal, g
process (sel, a, b)
begin
if sel = '1' then
f <= a;
g <= not a;
else
f = b;
g = a and b;
end if;
end process;
If statements can be nested if you have more complex behaviour to describe:
signal f, g : std_logic;
process (sel, sel_2, a, b)
begin
if sel = '1' then
f <= a;
if sel_2 = '1' then
g <= not a;
else
g <= not b;
end if;
else
if sel_2 = '1' then
g <= a and b;
else
g <= a or b;
end if;
f <= b;
end if;
end process;
Note that the order of assignments to f and g has been played around with (just to keep you on your toes!).
Synthesis considerations
If statements are synthesized by generating a multiplexer for each signal assigned within the if statement. The select input on each mux is driven by logic determined by the if condition, and the data inputs are determined by the expressions on the right hand sides of the assignments. During subsequent optimization by a synthesis tool, the multiplexer architecture may be changed to a structure using and-or-invert gates as surrounding functionality such as the and, or and not can be merged into complex and-or-invert gates to yield a more compact hardware implementation.
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