Let's turn our attention from re-usable code snippets to the coding of re-usable functions. We'll extend our parity process into a packaged function.
Remember that the parity generator was essentially coded as a for loop.
for i in a'RANGE loop
y := y xor a(i);
end loop;
This code can serve as the core of a parity function. The function will be expected to allow parity generators of arbitrary size to be implemented. In VHDL, arbitrarily-sized inputs to the parity function are supported by unconstrained array parameters. In use, the function may be called like this:
-- in the same architecture, a and b are std_logic_vector objects
p_out <= parity ("01101001"); -- a little odd, perhaps!
process
...
y := parity (a); -- a is 9 bits
...
end process;
-- b is 32 bits
p_32 <= parity (b);
In these three cases, the same function, parity, is being called, but in each case the width of the std_logic_vector passed to parity is different. The input parameter will need to be an unconstrained array.
library ieee;
use ieee.std_logic_1164.all;
-- analyze into library IO_processor
package bus_functions is
-- other subprogram declarations...
function parity (a: std_logic_vector) -- unconstrained array
return std_logic;
end bus_functions;
package body bus_functions is
-- other subprogram bodies...
function parity (a: std_logic_vector) return std_logic is
variable y : std_logic := '0';
begin
for i in a'RANGE loop
y := y xor a(i);
end loop;
return y;
end parity;
end bus_functions;
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