In this section, we look at writing the VHDL code to realise the testbench based on our earlier template.
Concurrent Assignment
The 5 concurrent signal assignment statements within the test bench define the input test vectors (eg. A <= 'X', '0' after 10 NS, '1' after 20 NS;). The delays in these assignments are relative to the time when the assignments execute (ie. time 0), not to each other (eg. Signal A will change to '1' at 20 NS, not at 30 NS).
Test Bench for MUX4
entity TEST_MUX4 is
end;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
architecture BENCH of TEST_MUX4 is
component MUX4
port (SEL :in STD_LOGIC_VECTOR(1 downto 0);
A, B, C, D:in STD_LOGIC;
F :out STD_LOGIC);
end component;
signal SEL: STD_LOGIC_VECTOR(1 downto 0);
signal A, B, C, D, F: STD_LOGIC;
begin
SEL <= "00", "01" after 30 NS, "10" after 60 NS,
"11" after 90 NS, "XX" after 120 NS,
"00" after 130 NS;
A <= 'X', '0' after 10 NS, '1' after 20 NS;
B <= 'X', '0' after 40 NS, '1' after 50 NS;
C <= 'X', '0' after 70 NS, '1' after 80 NS;
D <= 'X', '0' after 100 NS, '1' after 110 NS;
M: MUX4 port map (SEL, A, B, C, D, F);
end BENCH;
The waveforms generated for the SEL, A, B and C signals are shown below.
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