Doulos is pleased to again support Verification Futures Conference 2024 UK on Tuesday, June 18th in Reading (UK) and online.
This FREE one-day conference provides a unique blend of presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. It also gives an opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions.
Doulos Senior Member Technical Staff, Matthew Taylor will be presenting two sessions:
Introduction to Verification and SystemVerilog for Beginners
This presentation gives a brief overview of the current verification landscape, including verification objectives, simulation and formal verification approaches, the languages used and the tools required. It then introduces the main features of SystemVerilog – the most popular language used for verification today. This overview will provide a foundation for verification novices, who subsequently wish to study UVM or Formal Verification in greater detail. Read full description »
Is it easy to get started with UVM, or should I use Formal instead?
This presentation will introduce a subset of UVM, that makes it easier to get started and will show how these can be used to create a simple UVM testbench. However, a simulation-based approach is not always the best way to verify a design: Formal verification is also possible in SystemVerilog! The presentation will conclude with an overview of formal verification in SystemVerilog and consider how to decide the most appropriate approach to take. Read full description »
Find out more and register (FREE) for Verification Futures Conference 2024 UK »
