Global training solutions for engineers creating the world's electronics products

Arm Architecture Fundamentals Online

Duration: 2 sessions (4 hours per session)


PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.

This course is designed to provide hardware and software engineers, that are new to Arm® processors, with the essential basic information they will need to be aware of to start Arm-based designs. It can also be useful to non-technical staff who require a basic understanding of Arm technology.

 

  • A basic understanding of microprocessors or microcontrollers.
  • A basic understanding of assembler or C programming would be useful, but not essential.
  • No prior knowledge of the Arm processor is assumed.

The training materials for this class are based on Arm's own material.

Doulos is a global Arm Approved Training Partner.

  • Introduction to the Arm Architecture
    Architecture versions  • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future
  • Arm Cortex-A17 / A15 / A7 Overview
    Introduction • New Features in Cortex®-A17 / Cortex-A15 / Cortex-A7 • big/LITTLE Processing
  • Caches and Branch Prediction
    Caches basics • Arm Cache example • L1 and L2 Cache Interactions • Caching policies • Inner and Outer Caches • Cache Determinism • Maintenance and Coherency  • Branch Prediction
  • TrustZone®
    Why do we need a Secure environment? • Armv7-A Security Extensions • Software • Memory System • Debug
  • Architecture Overview
    Privilege levels • AArch64 registers • A64 Instruction Set • AArch64 Exception Model • AArch64 Memory Model
  • Software Engineer's Guide to the Arm Cortex-A72, Cortex-A57, Cortex-A53 and Cortex-A35 MPCore
    Core pipelines • Configuration options • Branch prediction • Cache overview • Data cache coherency • Memory management • Micro-architectural features • Interrupts and bus interfaces • Debug and timers • Big-little
  • Arm Cortex-M3/M4 Overview
    Block Diagram • Programmer’s Model • Datapath and Pipeline • Memory Map • Bit-Banding • System Timer (SysTick) • State, Privilege, and Stacks • Alignment and Endianness • System Control Block 

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