PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE. Please note for this course, daily sessions are up to 7 hours including breaks.
This training course is ideal for engineers involved in developing software for platforms powered by the Arm® Cortex®-A7/A15/A17 application processors.
The learning is reinforced with unique Lab exercises which are run inside a self contained virtual machine environment. This allows the student to experience a real-life and project-ready development environment without the complexity of installing complex software prior to the class. This virtual machine is for the student to keep after the training class, allowing you to further experiment with embedded software development once the class has come to completion.
This course is aimed at software developers writing low level and bare-metal code for Armv7-A processors, concentrating on the Cortex-A7/A15/A17 processor, and at operating system developers who need to understand the details of the Arm v7A processors' architecture.
Delegates should have some understanding of embedded programming in C and assembler. Knowledge of other processors is a benefit but is not strictly required for attending this class.
This class uses training materials developed by Arm® and is complemented by Doulos' own lecture and laboratory material. This offers the students a well rounded and practical view of the topics covering both the Processor's features along with how to program it.
Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future
Introduction • New Features in Cortex-A17 / Cortex-A15 / Cortex-A7 • big/LITTLE Processing
Load/Store • Data Processing • Flow Control • Misc • DSP
Introduction • Interrupts • Abort Handlers • SVC Handlers • Undef • Handlers • Reset Handlers
Caches basics • Arm Cache example • L1 and L2 Cache Interactions • Caching policies • Inner and Outer Caches • Cache Determinism • Maintenance and Coherency • Branch Prediction
L1 & L2 cache coherency and maintenance • MPCore • coherency
Introduction to atomicity • Load exclusive and store exclusive instructions • Code examples • Multi-core, coherency • Exclusive reservation granule
Short-descriptor Format • Long-descriptor Format • Memory Types and Attributes • Using the MMU
Data barriers • Instruction barriers
Arm core power modes • Power control • Arm multi-core processor power modes • Power state coordination
Overview • Booting a single CPU • Booting a cluster
Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations
Multi-Processing • Translation tables • Context switching • Timers
Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
Why do we need a Secure environment? • Armv7-A Security Extensions • Software • Memory System • Debug
Introduction • NEON Instruction Set Overview • NEON Software Support
Invasive Debug • Non-Invasive Debug • PMU • Trace
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues
Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries
Introduction • Multi-Cluster Configurations • Miscellaneous Considerations
Overview of Virtualization Extensions • Memory Management • Exception handling
The learning is reinforced with practical exercises using the GCC software development tool-chain and covers advanced topics such as Arm/Thumb2 assembly, writing low level device drivers, exception handlers and linker scripts.
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Enquiry FormPrice on request