Training duration: 3 sessions (6 hours per day)
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content, and delivers similar learning outcomes, as a scheduled in-person class.
Course Description
AMD Vitis™ Model Composer is the updated version of DSP System Generator and now provides support for HDL, HLS (High Level Synthesis) and AIE (AI Engine) development. Discover how this powerful combination of tools gives you the capability to develop advanced, low-cost DSP designs.
This course focuses on:
- Implementing DSP functions using Model Composer (MathWorks MATLAB® and Simulink®) for optimized FPGA IP
- Leveraging HLS support within Model Composer
- Utilizing design implementation tools
- Verifying through hardware co-simulation
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB and Simulink software and want to use AMD Model Composer and or Vitis HLS for DSP design.
- Experience with the MATLAB and Simulink software
- Overview of HLS design flow
- Basic understanding of sampling theory
- Vivado™ Design Suite System Edition
- Vitis Model Composer (formerly System Generator)
- Vitis HLS tool
- Vitis unified software platform
- MATLAB with Simulink software
- Architecture: 7 series and UltraScale™ FPGAs
- Demo board:Zynq® UltraScale+™ MPSoC ZCU104 board*
*Check with Doulos for the specifics of the in-class lab board or other customizations. The ZCU104 board is required for the "AXI4-Lite Interface Synthesis" lab.
After completing this comprehensive training, you will have the necessary skills to:
- Describe the Model Composer design flow for implementing DSP functions
- Identify AMD FPGA capabilities and how to implement a design from algorithm concept to hardware simulation
- List various low-level and high-level functional blocks available in Model Composer
- Run hardware co-simulation
- Identify the high-level blocks available for FIR and FFT designs
- Implement multi-rate systems in Model Composer
- Integrate optimized FPGA models into the Vivado IDE
- Design a processor-controllable interface for DSP
- Generate IPs from C-based design sources using the Vitis HLS tool for use in the Model Composer environment
- Create and simulate designs using Model Composer and HLS.
- Introduction to Model Composer
- Simulink Software Basics
- Lab 1: Using the Simulink Software
- Basic AMD Design Capture
- Lab 2: Getting Started with Model Composer
- Signal Routing
- Lab 3: Signal Routing
- Implementing System Control
- Multi-Rate Systems
- Lab 4: Designing a MAC-Based FIR
- Filter Design
- Lab 5: Designing a FIR Filter Using the FIR Compiler Block
- Intro to HLS Design Flow
- HLS Directives/Pragmas & IP Optimization
- HLS I/O Interface Optimization
- HLS dataflow and pipelining Optimization
- Model Composer, Vivado Design Suite, and Vitis HLS Integration
- Lab 6: Model Composer and Vitis HLS Tool Integration
- Importing C/C++ Code to Model Composer
- Lab 7: AXI4-Lite Interface Synthesis
- Lab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
- Lab 2: Getting Started with AMD Vitis Model Composer – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting an AMD evaluation board.
- Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.
- Lab 4: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using an AMD evaluation board.
- Lab 5: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using an AMD evaluation board.
- Lab 6: System Generator and Vitis HLS Tool Integration – Generate IP from a C-based design to use with System Generator.
- Lab 7: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq UltraScale+ MPSoC processor system. Then create and debug the application project using the Vitis IDE.
