AMD Device Architectures
- Introduction to FPGA Architecture, 3D ICs, Adaptive SoCs
Overview of FPGA architecture, SSI technology, etc.
Vivado Tool Flow
- Introduction to Vivado Project based Design Flows
Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE and simulating the design.
- Vivado Design Suite Non-Project-based Flow
Introduces the non-project-based flow in the Vivado Design Suite: creating a design, adding source files and simulating the design.
HDL Techniques
- RTL Development
Covers basic digital coding guidelines used in an FPGA design.
Vivado Synthesis and Implementation
- Vivado Synthesis and Implementation
Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board.
Design Analysis
- Introduction to Vivado Reports
Generate Vivado timing reports to analyze failed timing paths.
- Using Tcl Commands in the Vivado DS Project Flow
Explains what Tcl commands are executed in a Vivado Design Suite project flow.
Timing – Basics & Intermediate
- Introduction to Clock Constraints
Apply clock constraints and perform timing analysis.
- Generated Clocks
Use the report clock networks report to determine if there are any generated clocks in a design.
- I/O Constraints and Virtual Clocks
Apply I/O constraints and perform timing analysis.
- Setup and Hold Violation Analysis
Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis.
- Clock Group Constraints
Apply clock group constraints for asynchronous clock domains.
- Introduction to Timing Exceptions
Introduces timing exception constraints and applying them to fine tune design timing.
- Timing Constraints Editor
Introduces the timing constraints editor tool to create timing constraints.
Pin Planning
- Vivado Design Suite I/O Pin Planning
Use the I/O Pin Planning layout to perform pin assignments.
Power
- AMD Power Estimator Spreadsheet
Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
Design Techniques
- Synchronous Design Techniques
Introduces synchronous design techniques used in an FPGA design.
- Resets
Investigates the impact of using asynchronous resets in a design.
Clocking in the UltraScale and 7-Series Architecture
- Clocking Resources
Describes various clock resources, clocking layout, and routing in a design.
Clock buffers in the UltraScale and 7-Series Architecture
- Clock Buffers
Describes all clocking buffers including MMCM, BUFG, BUGCE, etc.
I/O in the UltraScale and 7-Series Architecture
- I/O Logic Resources
Overview of I/O resources and the IOB property for timing closure.
Debugging
- HDL Instantiation Debug Probing Flow
Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
IP Integrator
- Designing with the IP Integrator
Use the Vivado IP integrator to create the uart_led subsystem.
- Block Design Containers in the Vivado IP Integrator
Describes the block design container (BDC) feature and shows how to create a BDC in the IP integrator.
- Creating and Packaging Custom IP
Create your own IP and package and include it in the Vivado IP catalog.
- Using an IP Container
Use a core container file as a single file representation for an IP.
Debugging
- Introduction to the Vivado Logic Analyzer
Overview of the Vivado logic analyzer for debugging a design.
- Introduction to Triggering
Introduces the trigger capabilities of the Vivado logic analyzer.
- Debug Cores
Understand how the debug hub core is used to connect debug cores in a design.
Configuration
- Configuration Process
Reviews the FPGA configuration process, such as device power up, CRC checks, etc.
