High-Level Synthesis with the Vitis
HLS Tool

Software and hardware engineers looking to utilize high-level synthesis.

C or C++ knowledge

• Vitis HLS tool
• Vivado Design Suite
• Vitis unified software platform

Day 1

• Introduction to High-Level Synthesis
  Overview of high-level synthesis (HLS), the Vitis HLS tool flow,
  and the verification advantage. {Lecture}
• Vitis HLS Tool Flow
  Explores the basics of high-level synthesis and the Vitis HLS tool.
  {Lecture, Demo, Lab}
• Design Exploration with Directives
  Explores different optimization techniques that can improve the
  design performance. {Lecture}
• Vitis HLS Tool Command Line Interface
  Describes the Vitis HLS tool flow in command prompt mode.
  {Lecture, Lab}
• Introduction to HLS UltraFast Design Methodology
  Introduces the methodology guidelines covered in this course and
  the HLS UltraFast Design Methodology steps. {Lecture}
• Introduction to I/O Interfaces
  Explains interfaces such as the block-level and port-level
  protocols abstracted by the Vitis HLS tool from the C design.
  {Lecture}
• Block-Level I/O Protocols
  Explains the different types of block-level protocols abstracted by
  the Vitis HLS tool. {Lecture, Lab}
• Port-Level I/O Protocols
  Describes the port-level interface protocols abstracted by the Vitis
  HLS tool from the C design. {Lecture, Demo, Lab}
• Port-Level I/O Protocols: AXI4 Interfaces
  Explains the different AXI interfaces (such as AXI4-Master,
  AXI4-Lite (Slave), and AXI4-Stream) supported by the Vitis HLS
  tool. {Lecture, Demo}
• Port-Level I/O Protocols: Memory Interfaces
  Describes the memory interface port-level protocols (such as
  block RAM and FIFO) abstracted by the Vitis HLS tool from the C
  design. {Lecture, Lab}
• Pipeline for Performance: PIPELINE
  Describes the PIPELINE directive for improving the throughput of
  a design. {Lecture, Lab}

Day 2

• Pipeline for Performance: DATAFLOW
  Describes the DATAFLOW directive for improving the throughput
  of a design by pipelining the functions to execute as soon as
  possible. {Lecture, Lab}
• Optimizing Structures for Performance
  Identify the performance limitations caused by arrays in your
  design. You will also explore optimization techniques to handle
  arrays for improving performance. {Lecture, Demo, Lab}
• Vitis HLS Tool Default Behavior: Latency
  Describes the default behavior of the Vitis HLS tool on latency
  and throughput. {Lecture}
• Reducing Latency
  Describes how to optimize the C design to improve latency.
  {Lecture}
• Improving Area and Resource Utilization
  Describes different methods for improving resource utilization and
  explains how some of the directives have impact on the area
  utilization. {Lecture, Lab}
• Migrating to the Vitis HLS Tool
  Reviews key considerations when moving from the Vivado HLS
  tool to the Vitis HLS tool. {Lecture}
• HLS Design Flow – System Integration
  Describes the traditional RTL flow versus the Vitis HLS tool
  design flow. {Lecture, Lab}
• Vitis HLS Tool C Libraries: Arbitrary Precision
  Describes Vitis HLS tool support for the C/C++ languages as well
  as arbitrary precision data types. {Lecture, Lab}
• Hardware Modeling
  Describes hardware modeling with streaming data types and shift
  register implementation using the ap_shift_reg class. {Lecture}
• Using Pointers in the Vitis HLS Tool
  Explains the use of pointers in the design and workarounds for
  some of the limitations. {Lecture}