Training Duration: 5 sessions (4 hours per session)
This course comprises the following Xilinx Approved Training:
- PCIe Protocol Overview
- Designing an Integrated PCI Express System
This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content, and delivers similar learning outcomes, as a scheduled face-to face class.
The initial sessions of this training focus on the fundamentals of the Xilinx® PCI Express® protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed.
The training will then move on to provide a working knowledge of how to implement a PCI Express core in custom applications. This training offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This part of the course focuses on the AXI streaming interconnect.
- FPGA designers, logic designers, and anyone who needs an in-depth knowledge of the PCIe protocol
- Hardware designers who want to create applications using Xilinx IP cores for PCI Express® specification
- Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution
- System architects who want to leverage key Xilinx advantages related to performance, latency and bandwidth in PCI Express applications
- Moderate digital design experience
- Knowledge of VHDL or Verilog
- Some experience with Xilinx implementation tools and simulation tool, preferably the Vivado® simulator is useful
- Vivado® System Edition 2017.1
After completing this comprehensive training, you will know how to:
- Interpret various transactions occurring on the link
- Describe the layered architecture and the tasks and packet types each is responsible for
- Properly estimate maximum performance of a link
- Illustrate how errors can be communicated within the system
- Explain the relationship between Virtual Channels (VCs) and Traffic Class (TC) and the interaction with flow control credits
- Construct a basic PCIe system by:
- Selecting the appropriate core for your application
- Specifying requirements of an endpoint application
- Connecting this endpoint with the core
- Utilizing FPGA resources to support the core
- Simulating the design
- Identify the advanced capabilities of the PCIe specification protocol and feature set
- Course Introduction
- Introduction to PCIe Architecture
- Review of the PCIe Protocol
- Packet Formatting Details
- Lab 1: Packet Decoding [Delegate to complete after class.]
This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.
- Xilinx PCI Express Solutions
- Connecting Logic to the Core – AXI Interface
- PCIe Core Customization
- Packet Formatting Details
- Lab 2: Constructing the PCIe Core
This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
- Simulating a PCIe System Design
- Endpoint Application Considerations
- PCI Express in Embedded Systems
- Lab 3: Simulating the PCIe Core
This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets.
- Application Focus: DMA
- Design Implementation and PCIe Configuration
- Lab 4: Using the PCI Express Core in IP Integrator
This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.
- Root Port Applications
- Debugging and Compliance
- Interrupts and Error Management
- Course Summary