Comprehensive SystemC

• Hardware design engineers who wish to become skilled in the practical use of SystemC for modelling digital hardware
• System engineers and architects who wish to become skilled in the practical use of SystemC for system level modelling
• Software engineers who already have good knowledge of C/C++, but who wish to acquire some practical experience in the use of the SystemC class libraries

• The C++ language features necessary to master SystemC
• Object-oriented programming techniques as used by the SystemC class libraries
• The SystemC core language, data types and channels
• How to make best use of the SystemC simulator to debug and validate your models
• How to move up from RTL modelling to transaction-level modelling
• An introduction to the SystemC TLM-2.0 standard
• An overview of high-level synthesis using SystemC (optional)
• An overview of the SystemC Verification Library SCV (optional)

Essential C++ for SystemC 

Delegates need basic knowledge of the C programming language, in particular familiarity with C functions, variables, data types, operators, and statements. This module is suitable for people with no previous knowledge of C++, as a refresher for those with limited knowledge of C++, or for hardware engineers who are familiar with VHDL or Verilog®.

Fundamentals of SystemC 

A working knowledge of Modern C++ and object-oriented programming concepts is essential, and basic knowledge of hardware design is recommended. Prior attendance of the Doulos Essential C++ class (or equivalent) is required. Delegates with C++ experience should check their knowledge against the Essential C++ for SystemC course pre-requisites available from Doulos before attending. The course is suitable for electronic hardware, software or systems engineers, but in order to gain maximum benefit from this course, delegates should be active users of either a high-level software programming language (ideally C++) or a hardware description language (VHDL or Verilog®).

Please contact Doulos direct to discuss and assess your specific experience against the pre-requisites. 

Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include:

• Fully indexed class notes creating a complete reference manual
• Workbook full of practical examples and solutions to help you apply your knowledge
• Doulos SystemC Golden Reference Guide e-book for language, syntax, semantics and tips

If you would prefer a paperback version of your Doulos Golden Reference Guide, this can be purchased from the Doulos online shop.

Essential C++ for SystemC (2 Days)

From C to C++

Header files • Function overloading • Operator overloading • Pass-by-reference • const reference • Default arguments • I/O streams • Namespaces • Stream manipulators • Stream operator overloading • Standard string class • Stringstreams • Static, automatic, and dynamic storage • new and delete • attributes

Classes and Objects

Learn the principles of object-based design • Classes and objects • Inline members versus separate compilation • Public and private class members • Member functions • Scope resolution

Special Member Functions

Constructors • Destructors • Copy constructors • Initialization versus assignment • Pointers versus objects • The assignment operator • this • Constant objects and members

Vectors

Learn to make the most of the built-in standard classes • The C++ standard library • Vectors versus arrays • Common vector operations • Iterators

Subobjects

Class relationships • Subobjects versus pointers • Initializing members • Initializing const members

Inheritance

Learn to exploit the power of object-oriented programming • Derived classes • Inheritance • Protected members • Up- and down-casting

Virtual Functions

Delve deeper into object-oriented programming techniques • Overriding methods • Virtual functions • Polymorphism • Identifying types at run-time • Examples from SystemC • Abstract base classes

Templates and Conversions

Advanced C++ features used in the SystemC class libraries • Function templates • Class templates • Examples from SystemC • Implicit conversions • User-defined conversions

Extra Features

Friends • Static members • Order of initialization • Multiple inheritance • Exceptions

Fundamentals of SystemC (3 Days)

Introduction

Learn the background to SystemC and how SystemC fits into the system-level design flow • The architecture of the SystemC release • The benefits and risks of adopting SystemC • The objectives of transaction-level modeling

Getting Started

Learn how SystemC source code is structured and how to organize files • SystemC header files and namespaces • Compiling and executing a SystemC model

Modules and Channels

How to describe the structural connections between modules • Modules • Ports & Exports • Processes • Signals • Methods • Primitive channels • Module instantiation • Port binding

Processes and Time

Describing concurrency and the passage of time • SC_METHOD • SC_THREAD • Event finders • Static and dynamic sensitivity • Time • Events • Clocks • Dynamic processes

The Scheduler

Gain an insight into how SystemC manages the scheduling of processes and events • Starting and stopping simulation • Elaboration and simulation callbacks • The phases of simulation • Event notification • wait and next_trigger

SystemC Data Types

Data types for bit-accurate and hardware modeling • Signed and unsigned integers • Limited and finite precision integers • Assignment and truncation • Bit and part selects • Bit and logic vectors • Hexadecimal numbers

Debugging and Tracing

Learn about the facilities provided by SystemC to ease debugging and diagnostics • The report hander • Customizing report actions • Writing trace (vcd) files

Interfaces and Channels

Learn how channels are used to abstract communication and create fast simulation models • Hierarchical, primitive and minimal channels • Interface method calls • SystemC interfaces • Port-less channel access • The SystemC object hierarchy • The class sc_port • How to make the most of ports, channels and interfaces • sc_export

Bus modeling

Learn the techniques required to write and use bus models in SystemC • Master and slave interfaces • The execution context of interface method calls • Blocking and non-blocking methods • Using events and dynamic sensitivity within channels • Multi-ports • Port binding policies

More Core

sc_signal_resolved • register_port • sc_process_handle • Event finders • default_event • pos vs. posedge vs. posedge_event • sc_event_queue • request_update and update • Passing arguments to spawned processes • terminated_event

SystemC Vector

sc_vector

Introduction to TLM-2.0

Transaction Level Modeling • Virtual platforms • The architecture of TLM-2.0 • TLM-2.0 coding styles • The interoperability layer • TLM-2.0 utilities • Initiator, target, and interconnect • Initiator and target sockets • Generic payload • Response status 

Supplementary Reference Material

Process Control

enable • disable • suspend • resume • reset • kill • unwinding the call stack

Less Used

sc_writer_policy • sc_signal_resolved • sc_event_queue • sc_set_stop_mode

Cosimulation

sc_pending_activity • sc_pause • async_request_update

Fixed Point Types

Fixed point word length and integer word length • Quantization modes • Overflow modes • Fixed point context • The type cast switch • Utility methods 

Overview of the SystemC Verification Library

Introduction to and aims of SCV • Constrained random verification methodology • Extended data types to support introspection • Randomization • Transaction Recording 

SystemC RTL

Focuses on RTL features in SystemC.

Overview of SystemC Synthesis

RTL versus behavioural synthesis technology • The work of the OSCI synthesis working group • Synthesizable data types • Synthesis restrictions • Clocked threads and resets • Flow and outputs of behavioral synthesis

SystemC Engine

Step-by-step example of simulation details to aid understanding.