Introduction
Learn the background to SystemC and how SystemC fits into the system-level design flow • The architecture of the SystemC release • The benefits and risks of adopting SystemC • The objectives of transaction-level modeling
Getting Started
Learn how SystemC source code is structured and how to organize files • SystemC header files and namespaces • Compiling and executing a SystemC model
Modules and Channels
How to describe the structural connections between modules • Modules • Ports & Exports • Processes • Signals • Methods • Primitive channels • Module instantiation • Port binding
Processes and Time
Describing concurrency and the passage of time • SC_METHOD • SC_THREAD • Event finders • Static and dynamic sensitivity • Time • Events • Clocks • Dynamic processes
The Scheduler
Gain an insight into how SystemC manages the scheduling of processes and events • Starting and stopping simulation • Elaboration and simulation callbacks • The phases of simulation • Event notification • wait and next_trigger
SystemC Data Types
Data types for bit-accurate and hardware modeling • Signed and unsigned integers • Limited and finite precision integers • Assignment and truncation • Bit and part selects • Bit and logic vectors • Hexadecimal numbers
Debugging and Tracing
Learn about the facilities provided by SystemC to ease debugging and diagnostics • The report hander • Customizing report actions • Writing trace (vcd) files
Interfaces and Channels
Learn how channels are used to abstract communication and create fast simulation models • Hierarchical, primitive and minimal channels • Interface method calls • SystemC interfaces • Port-less channel access • The SystemC object hierarchy • The class sc_port • How to make the most of ports, channels and interfaces • sc_export
Bus modeling
Learn the techniques required to write and use bus models in SystemC • Master and slave interfaces • The execution context of interface method calls • Blocking and non-blocking methods • Using events and dynamic sensitivity within channels • Multi-ports • Port binding policies
More Core
sc_signal_resolved • register_port • sc_process_handle • Event finders • default_event • pos vs. posedge vs. posedge_event • sc_event_queue • request_update and update • Passing arguments to spawned processes • terminated_event
SystemC Vector
sc_vector
Introduction to TLM-2.0
Transaction Level Modeling • Virtual platforms • The architecture of TLM-2.0 • TLM-2.0 coding styles • The interoperability layer • TLM-2.0 utilities • Initiator, target, and interconnect • Initiator and target sockets • Generic payload • Response status
Supplementary Reference Material
Process Control
enable • disable • suspend • resume • reset • kill • unwinding the call stack
Less Used
sc_writer_policy • sc_signal_resolved • sc_event_queue • sc_set_stop_mode
Cosimulation
sc_pending_activity • sc_pause • async_request_update
Fixed Point Types
Fixed point word length and integer word length • Quantization modes • Overflow modes • Fixed point context • The type cast switch • Utility methods
Overview of the SystemC Verification Library
Introduction to and aims of SCV • Constrained random verification methodology • Extended data types to support introspection • Randomization • Transaction Recording
SystemC RTL
Focuses on RTL features in SystemC.
Overview of SystemC Synthesis
RTL versus behavioural synthesis technology • The work of the OSCI synthesis working group • Synthesizable data types • Synthesis restrictions • Clocked threads and resets • Flow and outputs of behavioral synthesis
SystemC Engine
Step-by-step example of simulation details to aid understanding.
