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PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content as a scheduled face-to face class and delivers comparable learning outcomes.
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Fundamentals of SystemC prepares you for the practical use of SystemC for transaction-level modelling. The class describes the core SystemC v2.2 class library and its application for system modelling, virtual platforms, and hardware implementation.
It includes an introduction to the SystemC TLM-2.0 standard which is taught in more detail in a separate 5 session follow-on class SystemC Modeling using TLM-2.0 online.
The workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and comprise approximately 50% of class time. Delegates can use the tools and platform of their choice on all exercises and workshops.
Important: The Fundamentals of SystemC course can only be attended if your C++ knowledge is proficient. To find out whether this is suitable for you, please contact Doulos.
Doulos has a world-wide lead in independent SystemC know-how having been active in SystemC-based methods since 2000. We have delivered SystemC training and support to engineers in more than 500 companies world-wide - including direct involvement with methodology and tool developers in such companies as Arm, Cadence, Seimens EDA and Synopsys.
Please contact Doulos direct to discuss and assess your specific experience against the pre-requisites.
Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include:
COVID NOTICE 2021:
Due to world-wide operational restrictions, Golden Reference Guides are not currently available in all regions. Course attendees will receive a reference guide as soon as possible once the pandemic situation improves.
Become proficient in using the features of SystemC
Learn the background to SystemC and how SystemC fits into the system-level design flow • The architecture of the SystemC release • The benefits and risks of adopting SystemC • The objectives of transaction-level modeling
Learn how SystemC source code is structured and how to organise files • SystemC header files and namespaces • Compiling and executing a SystemC model
Modules and Channels
How to describe the structural connections between modules • Modules • Ports • Processes • Signals • Methods • Primitive channels • Module instantiation • Port binding
Processes and Time
Describing concurrency and the passage of time • SC_METHOD • SC_THREAD • Event finders • Static and dynamic sensitivity • Time • Events • Clocks • Dynamic processes
Gain an insight into how SystemC manages the scheduling of processes and events • Starting and stopping simulation • Elaboration and simulation callbacks • The phases of simulation • Event notification • wait and next_trigger
Learn to apply SystemC to modeling data, communication and busses
SystemC Data Types
Data types for bit-accurate and hardware modeling • Signed and unsigned integers • Limited and finite precision integers • Assignment and truncation • Bit and part selects • Bit and logic vectors • Hexadecimal numbers
Debugging and Tracing
Learn about the facilities provided by SystemC to ease debugging and diagnostics • The report hander • Customizing report actions • Writing trace (vcd) files
Interfaces and Channels
Learn how channels are used to abstract communication and create fast simulation models • Hierarchical, primitive and minimal channels • Interface method calls • SystemC interfaces • Port-less channel access • The SystemC object hierarchy • The class sc_port • How to make the most of ports, channels and interfaces • sc_export
Learn the techniques required to write and use bus models in SystemC • Master and slave interfaces • The execution context of interface method calls • Blocking and non-blocking methods • Using events and dynamic sensitivity within channels • Multi-ports • Port binding policies
Exploration of the application of Transaction-Level modeling
sc_signal_resolved • register_port • sc_process_handle • Event finders • default_event • pos vs. posedge vs. posedge_event • sc_event_queue • request_update and update • Passing arguments to spawned processes • terminated_event • sc_set_stop_mode
Introduction to TLM-2.0
Transaction Level Modeling • Virtual platforms • The architecture of TLM-2.0 • TLM-2.0 coding styles • The interoperability layer • TLM-2.0 utilities • Initiator, target, and interconnect • Initiator and target sockets • Generic payload • Response status
Software execution and simulation • The time quantum • b_transport • Timing annotation • Temporal decoupling • The quantum keeper • Base protocol rules • DMI • Simple sockets • Extensions • Interoperability
Supplementary Reference Material
Fixed Point Types
Fixed point word length and integer word length • Quantization modes • Overflow modes • Fixed point context • The type cast switch • Utility methods
Overview of SystemC Synthesis
RTL versus behavioural synthesis technology • The work of the OSCI synthesis working group • Synthesizable data types • Synthesis restrictions • Clocked threads and resets
Overview of the SystemC Verification Library
Introduction to and aims of SCV • Constrained random verification methodology • Extended data types to support introspection • Randomization • Transaction Recording
An overview of the latest version of SystemC, that is, IEEE 1666-2011 and SystemC 2.3
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