Fundamentals of SystemC SELF-PACED

Intermediate Level - 24 hours (estimated completion time)
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PLEASE NOTE: This is a ONLINE SELF-PACED training.

Course Overview

Fundamentals of SystemC prepares you for the practical use of SystemC for transaction-level modelling. The class describes the core SystemC v2.2 class library and its application for system modelling, virtual platforms, and hardware implementation.

This self-paced training is only available via the Doulos Thinkific Learning Portal. Please contact your local Doulos team to discuss your training needs and how to access the course.

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Who is it for?

System engineers and architects who wish to become skilled in the practical use of SystemC for system level modelling
Software engineers who already have good knowledge of C/C++, but who wish to acquire some practical experience in the use of the SystemC class libraries

What will you learn?

How to make best use of the SystemC simulator to debug and validate your models
How to move up from RTL modelling to transaction-level modelling

Pre-requisites

A working knowledge of C++ and of object-oriented programming concepts is essential and basic knowledge of hardware design is recommended. Prior attendance of the Doulos Essential C++ class (or equivalent) is required. Delegates with C++ experience should check their knowledge against the SystemC C++ Pre-requisites available from Doulos before attending.

The course is suitable for electronic hardware, software or systems engineers, but in order to gain maximum benefit from this course, delegates should be active users of either a high-level software programming language (ideally C++) or a hardware description language (VHDL or Verilog®).

Please contact Doulos direct to discuss and assess your specific experience against the pre-requisites.

Course materials

Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include

Fully indexed class notes creating a complete reference manual
Workbook full of practical examples and solutions to help you apply your knowledge
Access to course exercises and worked solutions on the free and open EDA Playground platform.

Structure and Content

Introduction

Overview and background • Central concepts • The SystemC World • Use cases and benefits

Getting Started

Elementary SystemC syntax • Source code organisation • Running a simulation

Modules and Channels

Modules • Ports and signals • Primitive channels • Module instantiation • Port binding • Constructor arguments

Processes and Time

SC_METHOD and SC_THREAD • Static and dynamic sensitivity • Events and notification • Time • Clocks • Dynamic processes

The Scheduler

sc_start() • Elaboration and simulation callbacks • The SystemC scheduler • Event notification • wait() and next_trigger()

Debugging and Tracing

Debugging techniques • The report handler • Waveform tracing • sc_signal<user-defined-type>

Interfaces and Channels

The Interface Method Call • Implementing interfaces • Required and provided interfaces • Port-less channel access • Ports • Exports

Bus modeling

Master and slave interfaces • Blocking versus non-blocking • Static versus dynamic sensitivity • Multiports • end_of_elaboration()

Additional Features

Bus resolution • Multiple port bindings • Static and dynamic rule checking • Process handles • Event finders and methods that return events • Event queues and update requests • Passing arguments to spawned processes

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Fundamentals of SystemC Self-Paced

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