SystemVerilog for New Designers

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SystemVerilog for New Designers

SystemVerilog as a first or second language for FPGA or ASIC design
(Previously known as SystemVerilog for FPGA/ASIC Design)

This course is available Live Online worldwide: View the Live Online full course description »

Standard Level - 4 days

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SystemVerilog for New Designers prepares the engineer for practical project readiness for FPGA or ASIC design, including RTL synthesis, block-level test benches, and FPGA design flows. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects. While the emphasis is on the practical SystemVerilog-to-hardware flow for FPGA devices, this training course also provides the essential foundation needed by ASIC and FPGA designers wishing to go on to use the advanced features of SystemVerilog for functional verification.

SystemVerilog for New Designers is suitable for delegates with existing experience of Verilog or VHDL as well as for those who are learning SystemVerilog as their first hardware description language. For teams who are already skilled in Verilog or VHDL, this training course can be offered in a shortened form for on-site delivery. For verification teams who are looking to use the class-based features of SystemVerilog for constrained random functional verification, Doulos provides Modular SystemVerilog for in-house training options.

Workshops comprise approximately 50% of class time and are based around carefully designed exercises to reinforce and challenge the extent of learning.

Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:

Simulation

Aldec Active HDL™ & Riviera-PRO™
Cadence Xcelium®
Siemens EDA ModelSim® & Questa®
Synopsys VCS®

Synthesis

Synopsys Synplify Pro®
Synopsys Design Compiler®
Siemens EDA Precision® RTL

The course includes specific lab support for tool sets from the leading FPGA vendors including the vendor's native simulation and place-and-route tools.

The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.

What you will learn

The SystemVerilog language concepts and constructs essential for FPGA and ASIC design
How to write SystemVerilog for effective RTL synthesis
How to target SystemVerilog code to an FPGA device architecture
How to write simple and efficient SystemVerilog test benches
The tool flow from SystemVerilog through simulation, synthesis and FPGA place-and-route
How to write high quality SystemVerilog code that reflects best practice in the industry
How to write re-usable, parameterisable SystemVerilog code by exploiting parameters
How to run gate-level simulations

Who should attend?

Digital hardware design engineers who wish to learn how to use SystemVerilog for FPGA or ASIC hardware design at the register-transfer level (RTL) and for block-level verification.

Prerequisites

Delegates should have a good working knowledge of digital hardware design, or have attended Essential Digital Design Techniques (or equivalent). No previous SystemVerilog or Verilog knowledge is required.

Training materials

Doulos class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:

Fully indexed class notes creating a complete reference manual
Workbook full of practical examples and solutions to help you apply your knowledge
Doulos SystemVerilog Golden Reference Guide e-book for language, syntax, semantics and tips
Tool tour guides (to support the tools and technologies used on the course)

If you would prefer a paperback version of your Doulos Golden Reference Guide, this can be purchased from the Doulos online shop.

Structure and content

Introduction

The scope and application of SystemVerilog • Design and tool flow • FPGAs • Introduction to synthesis and synchronous design • SystemVerilog resources

Modules

Modules • Ports • Continuous assignments • Comments • Names • Design hierarchy • Module instantiation • Port connection shorthand • Test benches • Simple procedures

Numbers and formatting

Numbers • 2-valued & 4-valued logic • Vectors • Bit and part select • System calls • Output formatting • Time units • Always blocks • Ending simulation

Procedures - Event controls and If

initial & always • Event controls • if • begin & end • Combinational logic • always_comb • Incomplete assignment and latches • Unknowns and don't cares •

Procedures - Case and Loop

case • casez & casex • unique & priority • for • repeat • while • forever • break • continue • Integer variables

Clocks and Flip-flops

Synthesis of flip-flops and latches • Avoiding race hazards • Blocking & non-blocking assignments • Dealing with the scheduler and with clock skew • always_ff •Synchronous & asynchronous resets • Clock enables • Coding templates for synthesis • Flip-flop inference

Operators and Names

Bitwise, logical, reduction, and equality operators • Concatenation • Replication • Conditional operator • Hierarchical names

Memories

Array types • RAM coding style • Memory inference versus instantiation • $readmemb

Finite State Machines

State machines architecture • Coding styles for state machines • enum • State encoding • Unreachable states and input hazards

Types and Packages

Integer types • struct • packed • typedef • package • using • Scope resolution

Synthesis of Arithmetic and Counters

Arithmetic operators and their synthesis • signed & unsigned values • Resource sharing • Exploiting FPGA resources

File Organization and Parameterized Modules

Compilation units • Compiler directives • include • Macros • Conditional compilation • parameter • localparam • Parameter overriding • Parameterized modules • generate

Tasks and Functions

task • function • Argument passing • return • local declarations • automatic • Synthesis of tasks & functions

File I/O

Opening & closing files • Reading & writing files • The $display family • Using $fscanf •

Interfaces and Clocking Blocks

interface • Interface ports • modport • clocking • Clockvars • Clocking drives • Avoiding scheduler problems

Gate-Level Simulation

Libraries • SDF back-annotation • The DPI • force & release • Gate-level language constructs • Tristates & bus resolution

Looking for team-based training, or other locations?

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SystemVerilog for New Designers

Find a Training Course