Introduction
The scope and application of SystemVerilog • Design and tool flow • FPGAs • Introduction to synthesis and synchronous design • SystemVerilog resources
Modules
Modules • Ports • Continuous assignments • Comments • Names • Design hierarchy • Module instantiation • Port connection shorthand • Test benches • Simple procedures
Numbers and formatting
Numbers • 2-valued & 4-valued logic • Vectors • Bit and part select • System calls • Output formatting • Time units • Strings • Always blocks • Ending simulation
Always blocks and Synthesis
Overview of RTL Synthesis • Event controls • if • begin & end • Combinational logic • always_comb • Synthesis of flip-flops and latches • Avoiding race hazards • Blocking & non-blocking assignments • Dealing with the scheduler and with clock skew • always_ff •Synchronous & asynchronous resets • Clock enables • Incomplete assignment and latches • Conditional operator •
Procedural Statements
case • casez & casex • unique & priority • for • repeat • while • do • forever • break • continue • Labels • local variables
Operators and Names
Bitwise, logical, reduction, and equality operators • Concatenation • Replication • Shift operators • Hierarchical names
Finite State Machines
State machines architecture • Coding styles for state machines • enum • State encoding • Unreachable states and input hazards
Types and Packages
Integer types • vector arithmetic • signed & unsigned values • struct • packed • typedef • packed & unpacked arrays • modeling RAM • nets, ports & data types • package • using • Scope resolution
Randomization and Coverage
Constrained Random Verification • Random Numbers in SystemVerilog • std::randomize • Constraint Syntax •Functional Coverage • Covergroup Syntax • Coverage Bins • Cross Coverage
File Organization and Parameterized Modules
Compilation units • Compiler directives • include • Macros • Conditional compilation • parameter • localparam • Parameter overriding • Parameterized modules • generate
Tasks and Functions
task • function • Argument passing • return • local declarations • automatic
Interfaces
Simple Interface • Package versus Interface • Instantiating an Interface • Accessing Interface Members • Ports and Parameters on Interfaces • Pin-Level Interface • Modports • Generic Interface Ports • Task/Function in Interface • Calling Task through Interface Port
SystemVerilog Assertions
What are Properties? • Property versus Assertion • Immediate and Concurrent Assertions • Immediate Assertions • Assertion Failure Severity • Concurrent Assertions • Temporal Behaviour • Clocks and Default Clocks • Holds and Implication • Concatenation and Repetition • Simulation of Assertions
