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Seamless Refinement from Transaction Level to RTL Using SystemVerilog Interfaces

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The need for high-performance functional simulation of large system-on-chip designs, especially when the behavior of software is to be modeled in simulation, has given rise to a range of behavioral modeling styles that are often collectively known as transaction level modeling (TLM). A distinctive characteristic of TL models is the way in which they communicate with one another by means of subprogram calls. This form of module-to-module communication offers orders of magnitude performance improvement over the event-based communication used between modules in a traditional HDL simulation. Furthermore, because they operate at a much higher level of abstraction, TL models can be created and simulated long before synthesizable RTL code is available for testing.

TL modeling is often implemented in a general-purpose object-oriented programming language such as C++, and the existence of a widely accepted standard library (SystemC) has naturally increased the popularity of this approach. However, refinement from a SystemC design to synthesizable RTL code is unlikely to be automatic. Manual refinement is needed, followed by verification to check that the refinement was error-free. Unfortunately the resulting RTL design module is unlikely to operate successfully within the original TLM test environment, and so the successive steps in refinement cannot readily be verified within a common verification environment.

Our example exploits SystemVerilog interfaces to bridge this gap between RTL and TL models, enabling seamless interoperation between them in any reasonable combination whilst preserving the best possible simulation performance at each step in the refinement process. The paper shows how interfaces can allow TL and RTL models to work together, with any necessary adapter functionality encapsulated in the interface. An interface's subprogram import/export mechanism provides a means for transaction-level models to work with the interface, while other connected modules can use a traditional Verilog signal-level connection.

Using the VCS™ simulator, we will show a fully TL model constructed entirely using SystemVerilog, with some of the TL components then progressively replaced by conventional RTL modules without affecting other TL components that continue to participate in the simulation. In this way, seamless refinement is achieved in the sense that refining one module in the system from TL to RTL does not entail rebuilding of other parts of the system model.

The paper also considers how to combine the same interface mechanism with SystemVerilog's Direct Programming Interface (DPI) to integrate SystemC models into an otherwise SystemVerilog-based environment.