The Design CompilerTM synthesis tool from Synopsys, Inc. has two different console-mode user interfaces: the traditional dc_shell command language, and a Tcl shell which can be obtained by using the command dc_shell -t to launch the tool.
Design Compiler (DC) uses an internal database to store your design throughout the synthesis process. As you execute various DC commands to optimise and modify the synthesised design, the database is updated. Finally, when you are satisfied with the synthesised results, you can write the database out in some format such as EDIF, or as a Verilog or VHDL netlist.
When you use Tcl in DC you need to understand how DC exposes its database. Tcl can handle only string data, and of course the DC database is in a proprietary binary format, so your Tcl scripts must access the database through the commands and functions provided as part of DC. In particular it's very important to understand how DC allows you to group database objects into collections which can then be supplied as the arguments to various commands.
Doulos offers Tcl training including an optional module on Tcl in Synopsys DC, to give synthesis users a get-you-started overview of how to approach DC scripting.
One of the worked examples from our DC-Tcl module is a script that explores the DC design database, to any required depth of hierarchy, in order to locate the gate or module that drives a specified net. This could be useful, for example, as part of a script that adjusts the size of driver devices to suit the capacitive loading of the nets they drive.
This example script illustrates how to traverse the design hierarchy, and how to investigate the relationship between different objects (for example, discovering what net is connected to some pin of a module).