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Carry Look Ahead Blocks

This month's model provides the VHDL code for a set of three carry look ahead (CLA) blocks as used in a pipelined simultaneous multiplier design. These three blocks (for 4-, 5- and 6-bit operands) are used as building blocks in a set of two-stage block-carry CLA designs that deal with 25-, 26-, 28- and 29-bit operands.

The CLA blocks are designed to be used in larger block-carry designs or within fast adders. The second sample architecture shows the instantiation of smaller CLA blocks within a larger 14-bit two-stage block-carry design. The third sample architecture shows how the 14-bit CLA is instantiated in a 14-bit adder.

By their very nature, CLA blocks are required to be fast. Other fast carry structures are available that are inherently faster than CLA designs, for example carry select (CS) designs. However, they are much larger in terms of silicon area. For a given area budget, there is tradeoff to be made between pipelining a block-carry design versus an un-pipelined CS structure - this tradeoff usually favours the block-carry structure where pipelining is permitted.

In order to avoid the limitations of some synthesis tools when implementing fast carry structures, the VHDL is written at a very low level for these CLA blocks. There's still no substitute for good hardware design! The first sample architecture on this page presents the VHDL for a 4-bit CLA block. You'll need to download the files for the other CLA blocks. The architectures of all three are very similar, spot the differences!

Please note that we haven't provided all of the code for the 14-bit models, the presented samples are just to enable you to see how the CLA blocks are used.

You are welcome to use the source code we provide but you must keep the copyright notice with the code (see the Notices page for details).

The VFP Library is required for simulating this month's Model of the Month. To download the VFP files, click here.

First sample architecture : 4-bit CLA block

-- +-----------------------------+
-- |    Copyright 1996 DOULOS    |
-- |    Library :  arithmetic    |
-- |    designer : Tim Pagden    |
-- |     opened: 25 Jul 1996     |
-- +-----------------------------+

-- Architectures:
--   25.07.96 low_level

architecture low_level of cla_4 is

begin

  p_c0: process (p(0), g(0), c_in)
  begin
    c(0) <= (p(0) and c_in) or
            g(0);
  end process;

  p_c1: process (p(1 downto 0), g(1 downto 0), c_in)
  begin
    c(1) <= (p(1) and p(0) and c_in) or
            (p(1) and g(0)) or
            g(1);
  end process;

  p_c2: process (p(2 downto 0), g(2 downto 0), c_in)
  begin
    c(2) <= (p(2) and p(1) and p(0) and c_in) or
            (p(2) and p(1) and g(0)) or
            (p(2) and g(1)) or
            g(2);
  end process;

  p_c3: process (p(3 downto 0), g(3 downto 0), c_in)
  begin
    c(3) <= (p(3) and p(2) and p(1) and p(0) and c_in) or
            (p(3) and p(2) and p(1) and g(0)) or
            (p(3) and p(2) and g(1)) or
            (p(3) and g(2)) or
            g(3);
  end process;

  p_propogate: process (p)
  begin
    p_out <= p(0) and p(1) and p(2) and p(3);
  end process;

  p_generate: process (p(3 downto 1), g)
  begin
    g_out <= (p(3) and p(2) and p(1) and g(0)) or
             (p(3) and p(2) and g(1)) or
             (p(3) and g(2)) or
             g(3);
  end process;

end low_level;

end;

Second sample architecture : 14-bit CLA block

-- +-----------------------------+
-- |    Copyright 1996 DOULOS    |
-- |    Library :  arithmetic    |
-- |    designer : Tim Pagden    |
-- |     opened: 26 Jul 1996     |
-- +-----------------------------+

-- Architectures:
--   26.07.96 low_level

library arithmetic;

architecture low_level of cla_14 is
  use arithmetic.cla_2_cmpt.all;
  use arithmetic.cla_3_cmpt.all;
  use arithmetic.cla_4_cmpt.all;
  use arithmetic.cla_5_cmpt.all;

  signal p0, g0, c_0 : std_ulogic_vector(1 downto 0);
  signal p1, g1, c_1 : std_ulogic_vector(2 downto 0);
  signal p2, g2, c_2 : std_ulogic_vector(3 downto 0);
  signal p3, g3, c_3 : std_ulogic_vector(4 downto 0);
  signal c3, c7, c11, c15 : std_ulogic;

  signal p_0_0, g_0_0 : std_ulogic;
  signal p_0_1, g_0_1 : std_ulogic;
  signal p_0_2, g_0_2 : std_ulogic;
  signal p_0_3, g_0_3 : std_ulogic;
  signal p_0, g_0 : std_ulogic_vector(3 downto 0);

begin

  p0 <= p(1 downto 0);
  g0 <= g(1 downto 0);
  p1 <= p(4 downto 2);
  g1 <= g(4 downto 2);
  p2 <= p(8 downto 5);
  g2 <= g(8 downto 5);
  p3 <= p(13 downto 9);
  g3 <= g(13 downto 9);

  p_0 <= p_0_3 & p_0_2 & p_0_1 & p_0_0;
  g_0 <= g_0_3 & g_0_2 & g_0_1 & g_0_0;

  c <= c_3 & c_2 & c_1 & c_0;

  -- 0th rank, a set of 4 different width cla cells
  i0_0: cla_2
  port map (
    c_in  => c_in,
    p     => p0,
    g     => g0,
    c     => c_0,
    p_out => p_0_0,
    g_out => g_0_0
  );

  i0_1: cla_3
  port map (
    c_in  => c3,
    p     => p1,
    g     => g1,
    c     => c_1,
    p_out => p_0_1,
    g_out => g_0_1
  );

  i0_2: cla_4
  port map (
    c_in  => c7,
    p     => p2,
    g     => g2,
    c     => c_2,
    p_out => p_0_2,
    g_out => g_0_2
  );

  i0_3: cla_5
  port map (
    c_in  => c11,
    p     => p3,
    g     => g3,
    c     => c_3,
    p_out => p_0_3,
    g_out => g_0_3
  );

  -- 1st rank, a single cla cell
  i1_0: cla_4
  port map (
    c_in  => c_in,
    p     => p_0,
    g     => g_0,
    c(0)  => c3,
    c(1)  => c7,
    c(2)  => c11,
    c(3)  => c15,
    p_out => p_out,
    g_out => g_out
  );

end low_level;

Third sample architecture : 14-bit adder

-- +-----------------------------+
-- |    Copyright 1996 DOULOS    |
-- |    Library :  arithmetic    |
-- |    designer : Tim Pagden    |
-- |     opened: 27 Jul 1996     |
-- +-----------------------------+

-- Architectures:
--   27.07.96 low_level

library vfp;
library combinatorial;
library arithmetic;

architecture look_ahead of adder_14 is
  use vfp.bus_class.all;
  use combinatorial.xor_2_cmpt.all;
  use combinatorial.and_2_cmpt.all;
  use arithmetic.cla_14_cmpt.all;

  signal p: std_ulogic_vector(13 downto 0);
  signal g: std_ulogic_vector(13 downto 0);
  signal carry: std_ulogic_vector(13 downto 0);
  signal ab_in: ulogic_2_vector(13 downto 0);
  signal sum_in: ulogic_2_vector(13 downto 0);

begin

  pg: for i in 0 to 13 generate
    s0 : ab_in(i) <= a(i) & b(i);
    px: xor_2 port map (ab_in(i), p(i));
    ga: and_2 port map (ab_in(i), g(i));
    sum: xor_2 port map (sum_in(i), y(i));
    if_cin: if i = 0 generate
      s1 : sum_in(i) <= p(i) & c_in;
    end generate;
    if_cla_carry: if i /= 0 generate
      s1 : sum_in(i) <= p(i) & carry(i-1);
    end generate;
  end generate;

  cla: cla_14 port map (
    p     => p,
    g     => g,
    c_in  => c_in,
    c     => carry,
    p_out => open,
    g_out => open
  );

  c_out <= carry(13);

end look_ahead;

To download the VHDL source code for this month's Model of the Month, click here.

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