Many systems and ASICs depend upon a set of built-in values that ultimately control the nature of the code being written. For example, it would be likely that a testbench for a device being developed for the GSM phone system would contain the magic number 13e+6 at some point in the code:
constant gsm_clock : real := 13.0e6; constant pll_sys_clock : real := 2 * gsm_clock;
At a lower level counters and register designs incorporate magic numbers. The following code snippet (or a variation) is typically found in counters:
if RISING_EDGE(clock) then
if clear = '1' then
count := "00000000"; -- binary 0(others => '0')
or a linear-feedback shift register (LFSR):
if RISING_EDGE(clock) then
if new_value = "00000000" then -- binary 0
lfsr_reg := "11111111"; -- binary 255
For large vector literals, there is a better way to code up these magic numbers by using VHDL's others expression,
if RISING_EDGE(clock) then
if new_value = (others => '0') then -- binary 0
lfsr_reg := (others => '1'); -- binary 255
For more complex binary strings, you can still use the others expression. For example, supposing the magic number is 522 (number of weeks in a decade):
num_weeks_in_decade <= (9 => '1', 3 => '1', 1 => '1', others => '0');
This is an example of aggregate notation in VHDL. In this case an aggregate enables you to specify a value for a vector by specifying the values of individual elements of the vector. (Though at this point, "1000001010" is perhaps easier to write!).
For std_logic_vector objects, yes, you can write code like:
reg <= (63 => '1', 43 => 'Z', 26 => 'W', others => '0');
... although I am struggling to think of an application where you might want to write 64-bit vector code that mixes weak unknowns with tristate buffers!
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