Code re-use is often thought to mean designing re-usable components as parameterisable design entities. However, code re-use is a valid concept at all levels of abstraction.
In this example, we have a parity generator coded as a for loop. In the commented out code, the parity generator structure is fixed by the range constraint in the loop statement. In the uncommented code, the VHDL range attribute is used to create a parity generator structure which is proportional to the wordlength of the input data (a, in this case).
architecture ...
signal p_out : std_logic;
begin
PARITY: process (a)
variable y : std_logic;
begin
y := '0';
-- fixed width code
-- for i in 0 to 7 loop
-- y := y xor a(i);
-- end loop;
-- parameterisable code
for i in a'RANGE loop
y := y xor a(i);
end loop;
p_out <= y;
end process PARITY;
The advantage of the parameterisable code is that changes in the wordlength of a do not require a re-write of the PARITY process. Next, we will see how use of the range constraint is essential in creating a function with an unconstrained array parameter.
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